📄 l1_const.h
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/************* Revision Controle System Header *************
* GSM Layer 1 software
* L1_CONST.H
*
* Filename l1_const.h
* Copyright 2003 (C) Texas Instruments
*
************* Revision Controle System Header *************/
#ifdef __MSDOS__ // Running BORLANDC compiler.
#ifdef MVC
#define EXIT exit(0)
#define FAR
#else
#define EXIT DOS_Exit(0)
#define FAR far
#endif
#else // Running ARM compiler.
#define FAR
#define EXIT exit(0)
#define stricmp strcmp
#endif
#if (CODE_VERSION != SIMULATION)
#define NULL 0
#endif
#define NO_PAR 0
#define NO_TASK 0
#define ALL_TASK 0xffffffff
#define ALL_PARAM 0xffffffff
#define TRUE 1
#define TRUE_L 1L
#define FALSE 0
#define NOT_PENDING 0
#define PENDING 1
#define INACTIVE 2
#define ACTIVE 3
#define RE_ENTERED 4
#define WAIT_IQ 5
//---------------------------------------------
// MCU-DSP bit-field bit position definitions
//---------------------------------------------
#if L1_GPRS
#define GPRS_SCHEDULER 1 // Select GPRS scheduler
#endif
#define GSM_SCHEDULER 2 // Select GSM scheduler
//-----------------------------
// POWER MANAGEMENT............
//-----------------------------
#define MIN_SLEEP_TIME (SETUP_FRAME+2+l1_config.params.rf_wakeup_tpu_scenario_duration) //HW WAKE-UP+MIN_SLEEP(2)+AFC RESTORE(rf_wakeup_tpu_scenario_duration)
#define TPU_LOAD 01
#define TPU_FREEZE 02
// SLEEP ALGO SWITCH
#define NO_SLEEP 00 // ------ + ------ + ------
#define SMALL_SLEEP 01 // SMALL + ------ + ------
#define BIG_SLEEP 02 // ------ + BIG + ------
#define DEEP_SLEEP 03 // ------ + BIG + DEEP
#define ALL_SLEEP 04 // SMALL + BIG + DEEP
// GAUGING SAMPLES
#define SIZE_HIST 10
#define MAX_BAD_GAUGING 3
// GAUG_IN_32T = (HF in clock of 13Mhz*dpll) * ( LF in Khz)
#define GAUG_IN_32T 1348 // gauging duration is 1348*T32 measured on eva4
// DSP state need to be used to enter Deep Sleep mode
#if (W_A_DSP_IDLE3 == 1)
#define C_DSP_IDLE3 3
#endif
//-------------------------------------------------
// INIT: value is 32.768Khz at [-500 ppm, +100 ppm]
// to face temperature variation
//
// ACQUIS: variations allowed 32.768Khz +- 50 ppm
// 9 frames gauging is 1348*T32 (measured on eva4)
// UPDATE: variation allowed is +- 6 ppm jitter
//-------------------------------------------------
#define MCUCLK 13000 // 13 Mhz
#define LF 32.768
#define LF_100PPM 32.7712768 // 32.768*(1+100*10E-6)
#define LF_500PPM 32.751616 // 32.768*(1-500*10E-6)
#define LF_50PPM 32.7696384 // 32.768*(1+50*10E-6)
#define LF_6PPM 32.76819661 // 32.768*(1+6*10E-6)
#define NB_INIT 5 // nbr of gauging to pass to ACQUIS
#define NB_ACQU 10 // nbr of gauging to pass to UPDATE
#if (CHIPSET ==2 || CHIPSET ==3 || CHIPSET == 5 || CHIPSET == 6 || CHIPSET == 9) // PLL is at 65 Mhz !!!!!!
#define PLL 5 // 5*13Mhz = 65 Mhz
//-------------------------------------------------
// INIT: value is 32.768Khz at [-500 ppm, +100 ppm]
//
// ACQUIS: variations allowed 32.768Khz +- 50 ppm
// 9 frames gauging is 1348*T32 (measured on eva4)
// UPDATE: variation allowed is +- 6 ppm jitter
//-------------------------------------------------
#define C_CLK_MIN 1983 // 65000/32.7712768 = 1983.444234
#define C_CLK_INIT_MIN 29113 // 0.444234*2^16
#define C_CLK_MAX 1984 // 65000 / 32.751616 = 1984.634896
#define C_CLK_INIT_MAX 41608 // 0.634896*2^16
#define C_DELTA_HF_ACQUIS 130 // 1348/32.768-1348/32.7696384 = 0.002056632ms
// 0.002056632/0.0001538 = 130 T65Mhz
#define C_DELTA_HF_UPDATE 15 // 1348/32.768-1348/32.76819661 =0.00024691ms
// 0.00024691/0.0001538 = 15 T65Mhz
#endif
#define ARMIO_CLK_CUT 0x0001
#define UWIRE_CLK_CUT 0x0002
//-----------------------------
// Neighbour cell sync. reading
//-----------------------------
#if (L1_12NEIGH)
#define NBR_NEIGHBOURS 12
#else
#define NBR_NEIGHBOURS 6
#endif
//-----------------------------
// LAYER 1 MEASUREMENT TASKS...
//-----------------------------
#define NBR_L1S_MEAS_TASKS 4
#define FSMS 0
#define I_BAMS 1
#define D_BAMS 2
#define SERVMS 3
#define FSMS_MEAS (TRUE_L << FSMS) // Measurement task on FULL list (Cell Selection/Idle).
#define I_BAMS_MEAS (TRUE_L << I_BAMS) // Measurement task on BA list in Idle.
#define D_BAMS_MEAS (TRUE_L << D_BAMS) // Measurement task on BA list in Dedicated.
#define SERVMS_MEAS (TRUE_L << SERVMS) // Measurement task for Serving.
#define FSMS_MEAS_MASK ALL_TASK ^ FSMS_MEAS
#define I_BAMS_MEAS_MASK ALL_TASK ^ I_BAMS_MEAS
#define D_BAMS_MEAS_MASK ALL_TASK ^ D_BAMS_MEAS
#define SERVMS_MEAS_MASK ALL_TASK ^ SERVMS_MEAS
#define A_D_BLEN 456 // SACCH/SDCCH data block length (GSM 5.01 $7)
#define TCH_FS_BLEN 378 // TCH FULL SPEECH block length
#define TCH_HS_BLEN 211 // TCH HALF SPEECH block length
#define TCH_F_D_BLEN 456 // FACCH, TCH_DATA block length
#define MIN_ACCEPTABLE_SNR_FOR_SB 200 // threshold under which a SB shall be considered as not found
// Define max PM/TDMA according to DSP code and TPU RAM size
//----------------------------------------------------------
// NOTE: we should use a global variable initialized at L1 start and function of rx synth setup time.
#if ((CHIPSET == 2) || (CHIPSET == 3) || (CHIPSET == 4))
// TPU RAM size limitation
#define NB_MEAS_MAX 4
#define NB_MEAS_MAX_GPRS 4
#elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
// DSP code 33: upto 8 PMs with GSM and GPRS scheduler
#define NB_MEAS_MAX 8
#define NB_MEAS_MAX_GPRS 8
#elif (DSP == 32)
// DSP code prior to code 33 support upto 4 PMs with GSM scheduler
// and 8 PMs with GPRS scheduler, 6 for DSP 32 because of CPU load
#define NB_MEAS_MAX 4
#define NB_MEAS_MAX_GPRS 6
#else
// DSP code prior to code 33 support upto 4 PMs with GSM scheduler
// and 8 PMs with GPRS scheduler
#define NB_MEAS_MAX 4
#define NB_MEAS_MAX_GPRS 8
#endif
#endif
#if (AMR == 1)
#define SID_UPDATE_BLEN 212 // SID UPDATE block length
#define RATSCCH_BLEN 212 // RATSCCH block length
#define TCH_AFS_BLEN 448 // TCH Adaptative Full rate Speech block length
// Note: the d_nerr value is calculated thanks to the bit class 1 of the block.
// But the number AHS bit class 1 depends on the type of vocoder currently used (c.f. 5.03 &3.10.7.2)
#define TCH_AHS_7_95_BLEN 188 // TCH AHS 7.95 Speech block length
#define TCH_AHS_7_4_BLEN 196 // TCH AHS 7.4 Speech block length
#define TCH_AHS_6_7_BLEN 200 // TCH AHS 6.7 Speech block length
#define TCH_AHS_5_9_BLEN 208 // TCH AHS 5.9 Speech block length
#define TCH_AHS_5_15_BLEN 212 // TCH AHS 5.15 Speech block length
#define TCH_AHS_4_75_BLEN 212 // TCH AHS 4.75 Speech block length
#endif
//----------------------------------------
// LAYER 1 Asynchronous processes names...
//----------------------------------------
#if (L1_VOCODER_IF_CHANGE == 1)
#define NBR_L1A_PROCESSES 61 //increased to 60 from 59 for AAC
#else
#define NBR_L1A_PROCESSES 60 //increased to 60 from 61 for AAC
#endif
#define FULL_MEAS 0 // l1a_full_list_meas_process(msg)
#define CS_NORM 1 // l1a_cs_bcch_process(msg)
#define I_6MP 2 // l1a_idle_6strongest_monitoring_process(msg)
#define I_SCP 3 // l1a_idle_serving_cell_paging_process(msg)
#define I_SCB 4 // l1a_idle_serving_cell_bcch_reading_process(msg)
#define I_SMSCB 5 // l1a_idle_smscb_process(msg)
#define CR_B 6 // l1a_cres_process(msg)
#define ACCESS 7 // l1a_access_process(msg)
#define DEDICATED 8 // l1a_dedicated_process(msg)
#define I_FULL_MEAS 9 // l1a_dedicated_process(msg)
#define I_NMEAS 10 // l1a_idle_ba_meas_process(msg)
#define DEDIC_6 11 // l1a_dedic6_process(msg)
#define D_NMEAS 12 // l1a_dedic_ba_list_meas_process(msg)
#define HW_TEST 13 // l1a_test_process(msg)
#define I_BCCHN 14 // l1a_idle_neighbour_cell_bcch_reading_process(msg)
#define I_ADC 15 // l1a_mmi_adc_req(msg)
#define TMODE_FB0 16 // l1a_tmode_fb0_process(msg)
#define TMODE_FB1 17 // l1a_tmode_fb1_process(msg)
#define TMODE_SB 18 // l1a_tmode_sb_process(msg)
#define TMODE_BCCH 19 // l1a_tmode_bcch_reading_process(msg)
#define TMODE_RA 20 // l1a_tmode_access_process(msg)
#define TMODE_DEDICATED 21 // l1a_tmode_dedicated_process(msg)
#define TMODE_FULL_MEAS 22 // l1a_tmode_full_list_meas_process(msg)
#define TMODE_PM 23 // l1a_tmode_meas_process(msg)
#define TMODE_TRANSFER 24 // l1a_tmode_transfer_process(msg)
#define L1A_KEYBEEP_STATE 25 // l1a_mmi_keybeep_process(msg)
#define L1A_TONE_STATE 26 // l1a_mmi_tone_process(msg)
#define L1A_MELODY0_STATE 27 // l1a_mmi_melody0_process(msg)
#define L1A_MELODY1_STATE 28 // l1a_mmi_melody1_process(msg)
#define L1A_VM_PLAY_STATE 29 // l1a_mmi_vm_playing_process(msg)
#define L1A_VM_RECORD_STATE 30 // l1a_mmi_vm_recording_process(msg)
#define L1A_SR_ENROLL_STATE 31 // l1a_mmi_sr_enroll_process(msg)
#define L1A_SR_UPDATE_STATE 32 // l1a_mmi_sr_update_process(msg)
#define L1A_SR_RECO_STATE 33 // l1a_mmi_sr_reco_process(msg)
#define L1A_SR_UPDATE_CHECK_STATE 34 // l1a_mmi_sr_update_check_process(msg)
#define L1A_AEC_STATE 35 // l1a_mmi_aec_process(msg)
#define L1A_FIR_STATE 36 // l1a_mmi_fir_process(msg)
#define L1A_AUDIO_MODE_STATE 37 // l1a_mmi_audio_mode_process(msg)
#define L1A_MELODY0_E2_STATE 38 // l1a_mmi_melody0_e2_process(msg)
#define L1A_MELODY1_E2_STATE 39 // l1a_mmi_melody1_e2_process(msg)
#define L1A_VM_AMR_PLAY_STATE 40 // l1a_mmi_vm_amr_playing_process(msg)
#define L1A_VM_AMR_RECORD_STATE 41 // l1a_mmi_vm_amr_recording_process(msg)
#define L1A_CPORT_STATE 42 // l1a_mmi_cport_process(msg)
#define L1A_AUDIO_ONOFF_STATE 43 // l1a_mmi_audio_onoff_process(msg)
#define L1A_GTT_STATE 44 // l1a_mmi_gtt_process(msg)
#define INIT_L1 45 // l1a_init_layer1_process(msg)
#define HSW_CONF 46 // l1a_test_config_process(msg)
#define L1A_MP3_STATE 47 // l1a_mmi_mp3_process(msg)
#define TMODE_AUDIO_STEREOPATH_DRV_STATE 48 // l1a_tmode_audio_stereopath_process(msg)
#define L1A_EXT_AUDIO_MGT_STATE 49 // l1a_mmi_ext_audio_mgt_process(msg)
#define L1A_ANR_STATE 50 // l1a_mmi_anr_process(msg)
#define L1A_IIR_STATE 51 // l1a_mmi_iir_process(msg)
#define L1A_LIMITER_STATE 52 // l1a_mmi_limiter_process(msg)
#define L1A_ES_STATE 53 // l1a_mmi_es_process(msg)
#define L1A_MIDI_STATE 54 // l1a_mmi_midi_process(msg)
#define L1A_AGC_UL_STATE 55 // l1a_mmi_agc_ul_process(msg)
#define L1A_AGC_DL_STATE 56 // l1a_mmi_agc_dl_process(msg)
#define L1A_DRC_STATE 57 // l1a_mmi_drc_process(msg)
#define L1A_WCM_STATE 58 // l1a_mmi_wcm_process(msg)
#define L1A_AAC_STATE 59 // l1a_mmi_aac_process(msg)
#if (L1_VOCODER_IF_CHANGE == 1)
#define L1A_VOCODER_CFG_STATE 60 // l1a_mmi_vocoder_cfg_process
#endif
#if TESTMODE
#define TMODE_UPLINK (1<<0)
#define TMODE_DOWNLINK (1<<1)
#endif
//------------------------------------
// LAYER 1 DOWNLINK & UPLINK TASKS...
//------------------------------------
#define TASK_DISABLED 0
#define TASK_ENABLED 1
#define SEMAPHORE_RESET 0
#define SEMAPHORE_SET 1
#define NO_NEW_TASK -1
// Tasks in the order of their priority (low to high).
#if (GSM_IDLE_RAM != 0)
#define INT_RAM_GSM_IDLE_L1S_PROCESSES1 0x00000618 // PNP, PEP, NP, EP only are supported
#endif
#if !L1_GPRS
#define NBR_DL_L1S_TASKS 32
//GSM_TASKS/
#define HWTEST 0 // DSP checksum reading
#define ADC_CSMODE0 1 // ADC task in CS_MODE0 mode
#define DEDIC 2 // Global Dedicated mode switch
#define RAACC 3 // Channel access (ul)
#define RAHO 4 // Handover access (ul)
#define NSYNC 5 // Global Neighbour cell synchro switch
#define FBNEW 6 // Frequency burst search (Idle mode)
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