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📄 l1_tabs.h

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      { NULL,          0                  },  // DEDIC   (not meaningfull)
      { BLOC_RAACC,    BLOC_RAACC_SIZE    },  // RAACC                 
      { NULL,          0                  },  // RAHO    (not meaningfull)             
      { NULL,          0                  },  // NSYNC   (not meaningfull)             
      { BLOC_FBNEW,    BLOC_FBNEW_SIZE    },  // FBNEW 
      { BLOC_SBCONF,   BLOC_SBCONF_SIZE   },  // SBCONF 
      { BLOC_SB2,      BLOC_SB2_SIZE      },  // SB2 
      { BLOC_FB26,     BLOC_FB26_SIZE     },  // FB26               
      { BLOC_SB26,     BLOC_SB26_SIZE     },  // SB26
      { BLOC_SBCNF26,  BLOC_SBCNF26_SIZE  },  // SBCNF26
      { BLOC_FB51,     BLOC_FB51_SIZE     },  // FB51               
      { BLOC_SB51,     BLOC_SB51_SIZE     },  // SB51               
      { BLOC_SBCNF51,  BLOC_SBCNF51_SIZE  },  // SBCNF51               
      { BLOC_BCCHN,    BLOC_BCCHN_SIZE    },  // BCCHN   
      { BLOC_ALLC,     S_RECT4_SIZE       },  // ALLC
      { BLOC_EBCCHS,   S_RECT4_SIZE       },  // EBCCHS 
      { BLOC_NBCCHS,   S_RECT4_SIZE       },  // NBCCHS 
      { BLOC_SMSCB,    BLOC_SMSCB_SIZE    },  // SMSCB
      { BLOC_NP,       S_RECT4_SIZE       },  // NP  
      { BLOC_EP,       S_RECT4_SIZE       },  // EP  
      { BLOC_ADL,      S_RECT4_SIZE       },  // ADL
      { BLOC_AUL,      S_RECT4_SIZE       },  // AUL                 
      { BLOC_DDL,      S_RECT4_SIZE       },  // DDL
      { BLOC_DUL,      S_RECT4_SIZE       },  // DUL     
      { BLOC_TCHD,     BLOC_TCHT_SIZE     },  // TCHD
      { BLOC_TCHA,     BLOC_TCHA_SIZE     },  // TCHA
      { BLOC_TCHTF,    BLOC_TCHT_SIZE     },  // TCHTF
      { BLOC_TCHTH,    BLOC_TCHT_SIZE     },  // TCHTH
      { BLOC_BCCHN_TOP,BLOC_BCCHN_TOP_SIZE},  // BCCHN_TOP  
      { BLOC_SYNCHRO,  BLOC_SYNCHRO_SIZE  }   // SYNCHRO
    };

    const UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS] =
    {
      CHECKSUM_DSP_TASK,// HWTEST 
      0,                // DEDIC (not meaningfull)
      0,                // ADC   (not meaningfull)
      RACH_DSP_TASK,    // RAACC     
      RACH_DSP_TASK,    // RAHO
      0,                // NSYNC (not meaningfull)
      FB_DSP_TASK,      // FBNEW    
      SB_DSP_TASK,      // SBCONF
      SB_DSP_TASK,      // SB2     
      TCH_FB_DSP_TASK,  // FB26               
      TCH_SB_DSP_TASK,  // SB26               
      TCH_SB_DSP_TASK,  // SBCNF26               
      FB_DSP_TASK,      // FB51               
      SB_DSP_TASK,      // SB51               
      SB_DSP_TASK,      // SBCNF51               
      NBN_DSP_TASK,     // BCCHN         
      ALLC_DSP_TASK,    // ALLC      
      NBS_DSP_TASK,     // EBCCHS       
      NBS_DSP_TASK,     // NBCCHS       
      DDL_DSP_TASK,     // Temporary (BUG IN SIMULATOR)  CB_DSP_TASK,    // SMSCB
      NP_DSP_TASK,      // NP        
      EP_DSP_TASK,      // EP        
      ADL_DSP_TASK,     // ADL     
      AUL_DSP_TASK,     // AUL     
      DDL_DSP_TASK,     // DDL     
      DUL_DSP_TASK,     // DUL     
      TCHD_DSP_TASK,    // TCHD 
      TCHA_DSP_TASK,    // TCHA
      TCHT_DSP_TASK,    // TCHTF
      TCHT_DSP_TASK,    // TCHTH
      NBN_DSP_TASK,     // BCCHN_TOP == BCCHN
      0,                // SYNCHRO (not meaningfull)
    };                
  #else
    const T_TASK_MFTAB  TASK_ROM_MFTAB[NBR_DL_L1S_TASKS] =
    {
      { BLOC_HWTEST,       BLOC_HWTEST_SIZE  },       // HWTEST 
      { BLOC_ADC,          BLOC_ADC_SIZE     },       // ADC in CS_MODE0
      { NULL,              0                 },       // DEDIC   (not meaningfull)
      { BLOC_RAACC,        BLOC_RAACC_SIZE   },       // RAACC                 
      { NULL,              0                 },       // RAHO    (not meaningfull)
      { NULL,              0                 },       // NSYNC   (not meaningfull)             
      { BLOC_POLL ,        BLOC_POLL_SIZE    },       // POLL
      { BLOC_PRACH,        BLOC_PRACH_SIZE   },       // PRACH  
      { BLOC_ITMEAS,       BLOC_ITMEAS_SIZE  },       // ITMEAS 
      { BLOC_FBNEW,        BLOC_FBNEW_SIZE   },       // FBNEW 
      { BLOC_SBCONF,       BLOC_SBCONF_SIZE  },       // SBCONF 
      { BLOC_SB2,          BLOC_SB2_SIZE     },       // SB2 
      { BLOC_PTCCH,        BLOC_PTCCH_SIZE   },       // PTCCH  
      { BLOC_FB26,         BLOC_FB26_SIZE    },       // FB26               
      { BLOC_SB26,         BLOC_SB26_SIZE    },       // SB26
      { BLOC_SBCNF26,      BLOC_SBCNF26_SIZE },       // SBCNF26
      { BLOC_FB51,         BLOC_FB51_SIZE    },       // FB51               
      { BLOC_SB51,         BLOC_SB51_SIZE    },       // SB51               
      { BLOC_SBCNF51,      BLOC_SBCNF51_SIZE },       // SBCNF51
      { BLOC_PDTCH,        BLOC_PDTCH_SIZE   },       // PDTCH   
      { BLOC_BCCHN,        BLOC_BCCHN_SIZE   },       // BCCHN   
      { BLOC_ALLC,         S_RECT4_SIZE      },       // ALLC
      { BLOC_EBCCHS,       S_RECT4_SIZE      },       // EBCCHS 
      { BLOC_NBCCHS,       S_RECT4_SIZE      },       // NBCCHS 
      { BLOC_ADL,          S_RECT4_SIZE      },       // ADL
      { BLOC_AUL,          S_RECT4_SIZE      },       // AUL                 
      { BLOC_DDL,          S_RECT4_SIZE      },       // DDL
      { BLOC_DUL,          S_RECT4_SIZE      },       // DUL     
      { BLOC_TCHD,         BLOC_TCHT_SIZE    },       // TCHD
      { BLOC_TCHA,         BLOC_TCHA_SIZE    },       // TCHA
      { BLOC_TCHTF,        BLOC_TCHT_SIZE    },       // TCHTF
      { BLOC_TCHTH,        BLOC_TCHT_SIZE    },       // TCHTH
      { BLOC_PALLC,        BLOC_PCCCH_SIZE   },       // PALLC
      { BLOC_SMSCB,        BLOC_SMSCB_SIZE   },       // SMSCB
      { BLOC_PBCCHS,       BLOC_PBCCHS_SIZE  },       // PBCCHS
      { BLOC_PNP,          BLOC_PCCCH_SIZE   },       // PNP
      { BLOC_PEP,          BLOC_PCCCH_SIZE   },       // PEP
      { BLOC_SINGLE,       BLOC_SINGLE_SIZE  },       // SINGLE        
      { BLOC_PBCCHN_TRAN,  BLOC_PBCCHN_TRAN_SIZE },   // PBCCHN_TRAN   
      { BLOC_PBCCHN_IDLE,  BLOC_PBCCHN_IDLE_SIZE },   // PBCCHN_IDLE   
      { BLOC_BCCHN_TRAN,   BLOC_BCCHN_TRAN_SIZE },    // BCCHN_TRAN  
      { BLOC_NP,           S_RECT4_SIZE      },       // NP  
      { BLOC_EP,           S_RECT4_SIZE      },       // EP  
      { BLOC_BCCHN_TOP,    BLOC_BCCHN_TOP_SIZE},      // BCCHN_TOP  
      { BLOC_SYNCHRO,      BLOC_SYNCHRO_SIZE }        // SYNCHRO
    };

    const UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS] =
    {
      CHECKSUM_DSP_TASK,// HWTEST 
      0,                // ADC   (not meaningfull)
      0,                // DEDIC (not meaningfull)
      RACH_DSP_TASK,    // RAACC     
      RACH_DSP_TASK,    // RAHO
      0,                // NSYNC  (not meaningfull)
      0,                // POLL   (not meaningfull)
      0,                // PRACH  (not meaningfull)
      0,                // ITMEAS 
      FB_DSP_TASK,      // FBNEW    
      SB_DSP_TASK,      // SBCONF
      SB_DSP_TASK,      // SB2     
      PTCCHU_DSP_TASK,  // PTCCH  
      TCH_FB_DSP_TASK,  // FB26               
      TCH_SB_DSP_TASK,  // SB26               
      TCH_SB_DSP_TASK,  // SBCNF26               
      FB_DSP_TASK,      // FB51               
      SB_DSP_TASK,      // SB51               
      SB_DSP_TASK,      // SBCNF51               
      0,                // PDTCH  (not meaningfull)
      NBN_DSP_TASK,     // BCCHN         
      ALLC_DSP_TASK,    // ALLC      
      NBS_DSP_TASK,     // EBCCHS       
      NBS_DSP_TASK,     // NBCCHS       
      ADL_DSP_TASK,     // ADL     
      AUL_DSP_TASK,     // AUL     
      DDL_DSP_TASK,     // DDL     
      DUL_DSP_TASK,     // DUL     
      TCHD_DSP_TASK,    // TCHD 
      TCHA_DSP_TASK,    // TCHA
      TCHT_DSP_TASK,    // TCHTF
      TCHT_DSP_TASK,    // TCHTH
      0,                // PALLC  (not meaningfull)
      DDL_DSP_TASK,     // Temporary (BUG IN SIMULATOR)  CB_DSP_TASK,    // SMSCB
      DDL_DSP_TASK,     // PBCCHS (In order to allow PBCCHS running in CS or Idle mode, we have to specify a valid DSP task in order to request a PBCCHS with the GSM scheduler)
      0,                // PNP    (not meaningfull)
      0,                // PEP    (not meaningfull)
      0,                // SINGLE (not meaningfull) 
      0,                // PBCCHN_TRAN (not meaningfull)    
      DDL_DSP_TASK,     // PBCCHN_IDLE (only for GSM scheduler the task used is the same as SMSCB task)
      NBN_DSP_TASK,     // BCCHN_TRAN == BCCHN
      NP_DSP_TASK,      // NP        
      EP_DSP_TASK,      // EP        
      NBN_DSP_TASK,     // BCCHN_TOP == BCCHN
      0                 // SYNCHRO (not meaningfull)
    };                

  #endif

    const UWORD8 REPORTING_PERIOD[] =
    {
      255,            // INVALID_CHANNEL -> invalid reporting period
      104,            // TCH_F              
      104,            // TCH_H              
      102,            // SDCCH_4            
      102             // SDCCH_8            
    }; 
    
    const UWORD8 TOA_PERIOD_LEN[] =
    {
      0,              // CS_MODE0 not used for histogram filling       
      12,             // CS_MODE histogram length            
      12,             // I_MODE histogram length            
      12,             // CON_EST_MODE1 histogram length  
     144,             // CON_EST_MODE2 histogram length      
      36,             // DEDIC_MODE (Full rate) histogram length        
      42,             // DEDIC_MODE (Half rate) histogram length        
      #if L1_GPRS
        16,           // PACKET TRANSFER MODE histogram length
      #endif
    }; 
    
   // #if (STD == GSM) 
      const UWORD8 MIN_TXPWR_GSM[] =
      {
        0,  // unused.
        0,  // Power class = 1, unused for GSM900
        2,  // Power class = 2.
        3,  // Power class = 3.
        5,  // Power class = 4.
        7   // Power class = 5.
      };
   // #elif (STD == PCS1900)
      const UWORD8 MIN_TXPWR_PCS[] =
      {
        0,  // unused.
        0,  // Power class = 1.
        3,  // Power class = 2.
       30   // Power class = 3.
      };
   // #elif (STD == DCS1800)
      const UWORD8 MIN_TXPWR_DCS[] =
      {
        0,  // unused.
        0,  // Power class = 1.
        3,  // Power class = 2.
       29   // Power class = 3.
      };

       const UWORD8 MIN_TXPWR_GSM850[] =
      {
        0,  // unused.
        0,  // Power class = 1, unused for GSM900
        2,  // Power class = 2.
        3,  // Power class = 3.
        5,  // Power class = 4.
        7   // Power class = 5.
      };

  //  #elif (STD == DUAL)
   //   const UWORD8 MIN_TXPWR_GSM[] =
   //  {
   //     0,  // unused.
   //     0,  // Power class = 1, unused for GSM900
   //     2,  // Power class = 2.
   //     3,  // Power class = 3.
   //     5,  // Power class = 4.
   //     7   // Power class = 5.
   //   };
   //   const UWORD8 MIN_TXPWR_DCS[] =
   //   {
   //     0,  // unused.
   //     0,  // Power class = 1.
   //     3,  // Power class = 2.
   //    29   // Power class = 3.
   //   };
  //  #endif

  const UWORD8 GAUG_VS_PAGING_RATE[] =
  {
    4,   // bs_pa_mfrms = 2, 1 gauging every 4 Paging blocs
    3,   // bs_pa_mfrms = 3, 1 gauging every 3 Paging blocs
    2,   // bs_pa_mfrms = 4, 1 gauging every 2 Paging blocs
    1,   // bs_pa_mfrms = 5, 1 gauging every 1 Paging bloc
    1,   // bs_pa_mfrms = 6, 1 gauging every 1 Paging bloc
    1,   // bs_pa_mfrms = 7, 1 gauging every 1 Paging bloc
    1,   // bs_pa_mfrms = 8, 1 gauging every 1 Paging bloc
    1    // bs_pa_mfrms = 9, 1 gauging every 1 Paging bloc
  };   
    
  #else
    extern T_IDLE_TASK_INFO IDLE_INFO_COMB[(MAX_AG_BLKS_RES_COMB+1) * (MAX_PG_BLOC_INDEX_COMB+1)];
    extern T_IDLE_TASK_INFO IDLE_INFO_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1) * (MAX_PG_BLOC_INDEX_NCOMB+1)];
    extern UWORD8           NBPCH_IN_MF51_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1)];
    extern UWORD8           NBPCH_IN_MF51_COMB[(MAX_AG_BLKS_RES_COMB+1)];
    extern UWORD8           DSC_INIT_VALUE[MAX_BS_PA_MFRMS-2];
    extern T_SDCCH_DESC     SDCCH_DESC_NCOMB[];
    extern T_SDCCH_DESC     SDCCH_DESC_COMB[];
    extern UWORD8           RNTABLE[114];
    extern UWORD8           COMBINED_RA_DISTRIB[51];
    extern T_TASK_MFTAB     TASK_ROM_MFTAB[NBR_DL_L1S_TASKS];
    extern UWORD8           DSP_TASK_CODE[NBR_DL_L1S_TASKS];
    extern UWORD8           REPORTING_PERIOD[];
    extern UWORD8           TOA_PERIOD_LEN[];
    extern UWORD8           MIN_TXPWR_GSM[];
    extern UWORD8           MIN_TXPWR_DCS[];
    extern UWORD8           MIN_TXPWR_PCS[];
    extern UWORD8           MIN_TXPWR_GSM850[];
    extern UWORD8           GAUG_VS_PAGING_RATE[];
  #endif
#endif //L1_TABS_H

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