📄 bspuicc_phy_llif.h
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#define BSP_UICC_PHY_LLIF_MASK_USIM_WT_WIDTH 1
#define BSP_UICC_PHY_LLIF_MASK_USIM_OV_OFFSET 2
#define BSP_UICC_PHY_LLIF_MASK_USIM_OV_WIDTH 1
#define BSP_UICC_PHY_LLIF_MASK_USIM_TX_OFFSET 3
#define BSP_UICC_PHY_LLIF_MASK_USIM_TX_WIDTH 1
#define BSP_UICC_PHY_LLIF_MASK_USIM_RX_OFFSET 4
#define BSP_UICC_PHY_LLIF_MASK_USIM_RX_WIDTH 1
#define BSP_UICC_PHY_LLIF_MASK_USIM_CD_OFFSET 5
#define BSP_UICC_PHY_LLIF_MASK_USIM_CD_WIDTH 1
#define BSP_UICC_PHY_LLIF_MASK_USIM_EOB_OFFSET 6
#define BSP_UICC_PHY_LLIF_MASK_USIM_EOB_WIDTH 1
#define BSP_UICC_PHY_LLIF_MASK_USIM_TOC_OFFSET 7
#define BSP_UICC_PHY_LLIF_MASK_USIM_TOC_WIDTH 1
#define BSP_UICC_PHY_LLIF_MASK_USIM_TOB_OFFSET 8
#define BSP_UICC_PHY_LLIF_MASK_USIM_TOB_WIDTH 1
#define BSP_UICC_PHY_LLIF_MASK_USIM_RESENT_OFFSET 9
#define BSP_UICC_PHY_LLIF_MASK_USIM_RESENT_WIDTH 1
#define BSP_UICC_PHY_LLIF_MASK_USIM_TS_ERROR_OFFSET 10
#define BSP_UICC_PHY_LLIF_MASK_USIM_TS_ERROR_WIDTH 1
#define BSP_UICC_PHY_LLIF_MASK_EMV_ATR_LEN_TO_OFFSET 11
#define BSP_UICC_PHY_LLIF_MASK_EMV_ATR_LEN_TO_WIDTH 1
#define BSP_UICC_PHY_LLIF_REG_USIM_MASKIT_OFFSET 0
#define BSP_UICC_PHY_LLIF_REG_USIM_MASKIT_WIDTH 16
#define BSP_UICC_PHY_LLIF_INTERRUPT_MASK_ALL 0xFFF
#define BSP_UICC_PHY_LLIF_INTERRUPT_MASK 1
#define BSP_UICC_PHY_LLIF_INTERRUPT_UNMASK 0
/****** Definitions for USIM_DRX Register **********/
#define BSP_UICC_PHY_LLIF_USIM_DRX_OFFSET 0
#define BSP_UICC_PHY_LLIF_USIM_DRX_WIDTH 8
#define BSP_UICC_PHY_LLIF_USIM_STATRXPAR_OFFSET 8
#define BSP_UICC_PHY_LLIF_USIM_STATRXPAR_WIDTH 1
#define BSP_UICC_PHY_LLIF_REG_USIM_DRX_OFFSET 0
#define BSP_UICC_PHY_LLIF_REG_USIM_DRX_WIDTH 9
/****** Definitions for USIM_DTX Register **********/
#define BSP_UICC_PHY_LLIF_REG_USIM_DTX_OFFSET 0
#define BSP_UICC_PHY_LLIF_REG_USIM_DTX_WIDTH 8
/****** Definitions for USIM_FIFOS Register ********/
#define BSP_UICC_PHY_LLIF_FIFO_DMA_MODE_OFFSET 0
#define BSP_UICC_PHY_LLIF_FIFO_DMA_MODE_WIDTH 1
#define BSP_UICC_PHY_LLIF_FIFO_ENABLE_OFFSET 1
#define BSP_UICC_PHY_LLIF_FIFO_ENABLE_WIDTH 1
#define BSP_UICC_PHY_LLIF_FIFO_TX_TRIGGER_OFFSET 2
#define BSP_UICC_PHY_LLIF_FIFO_TX_TRIGGER_WIDTH 4
#define BSP_UICC_PHY_LLIF_FIFO_TX_RESET_OFFSET 6
#define BSP_UICC_PHY_LLIF_FIFO_TX_RESET_WIDTH 1
#define BSP_UICC_PHY_LLIF_FIFO_TX_EMPTY_OFFSET 7
#define BSP_UICC_PHY_LLIF_FIFO_TX_EMPTY_WIDTH 1
#define BSP_UICC_PHY_LLIF_FIFO_TX_FULL_OFFSET 8
#define BSP_UICC_PHY_LLIF_FIFO_TX_FULL_WIDTH 1
#define BSP_UICC_PHY_LLIF_FIFO_RX_TRIGGER_OFFSET 9
#define BSP_UICC_PHY_LLIF_FIFO_RX_TRIGGER_WIDTH 4
#define BSP_UICC_PHY_LLIF_FIFO_RX_RESET_OFFSET 13
#define BSP_UICC_PHY_LLIF_FIFO_RX_RESET_WIDTH 1
#define BSP_UICC_PHY_LLIF_FIFO_RX_EMPTY_OFFSET 14
#define BSP_UICC_PHY_LLIF_FIFO_RX_EMPTY_WIDTH 1
#define BSP_UICC_PHY_LLIF_FIFO_RX_FULL_OFFSET 15
#define BSP_UICC_PHY_LLIF_FIFO_RX_FULL_WIDTH 1
#define BSP_UICC_PHY_LLIF_REG_USIM_FIFOS_OFFSET 0
#define BSP_UICC_PHY_LLIF_REG_USIM_FIFOS_WIDTH 16
enum
{
BSP_UICC_PHY_LLIF_FIFO_DISABLE = 0,
BSP_UICC_PHY_LLIF_FIFO_ENABLE = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_FifoEnable;
enum
{
BSP_UICC_PHY_LLIF_FIFO_OPT_TX_TRIG_SIZE = 3,
BSP_UICC_PHY_LLIF_FIFO_MAX_TX_SIZE = 0x9
};
typedef SYS_UWORD8 BspUicc_Usim_llif_FifoTxTriggerSize;
enum
{
BSP_UICC_PHY_LLIF_FIFO_MIN_RX_TRIG_SIZE = 1,
BSP_UICC_PHY_LLIF_FIFO_OPT_RX_TRIG_SIZE = 0xD
};
typedef SYS_UWORD8 BspUicc_Usim_llif_FifoRxTriggerSize;
enum
{
BSP_UICC_PHY_LLIF_FIFO_TX_RESET_DISABLE = 0,
BSP_UICC_PHY_LLIF_FIFO_TX_RESET_ENABLE = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_FifoTxReset;
enum
{
BSP_UICC_PHY_LLIF_FIFO_TX_EMPTY_DISABLED= 0,
BSP_UICC_PHY_LLIF_FIFO_TX_EMPTY_ENABLED = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_FifoTxEmpty;
enum
{
BSP_UICC_PHY_LLIF_FIFO_TX_FULL_DISABLED = 0,
BSP_UICC_PHY_LLIF_FIFO_TX_FULL_ENABLED = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_FifoTxFull;
enum
{
BSP_UICC_PHY_LLIF_FIFO_RX_RESET_DISABLE = 0,
BSP_UICC_PHY_LLIF_FIFO_RX_RESET_ENABLE = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_FifoRxReset;
enum
{
BSP_UICC_PHY_LLIF_FIFO_RX_EMPTY_DISABLED = 0,
BSP_UICC_PHY_LLIF_FIFO_RX_EMPTY_ENABLED = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_FifoRxEmpty;
enum
{
BSP_UICC_PHY_LLIF_FIFO_RX_FULL_DISABLED = 0,
BSP_UICC_PHY_LLIF_FIFO_RX_FULL_ENABLED = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_FifoRxFull;
/****** Definitions for USIM_CGT Register ********/
#define BSP_UICC_PHY_LLIF_USIM_CGT_OFFSET 0
#define BSP_UICC_PHY_LLIF_USIM_CGT_WIDTH 8
typedef SYS_UWORD8 BspUicc_Usim_llif_UsimCgt;
/****** Definitions for USIM_CWT Register ********/
#define BSP_UICC_PHY_LLIF_USIM_CWT_OFFSET 0
#define BSP_UICC_PHY_LLIF_USIM_CWT_WIDTH 16
typedef SYS_UWORD16 BspUicc_Usim_llif_UsimCwt;
/****** Definitions for USIM_BWT_LSB Register ********/
#define BSP_UICC_PHY_LLIF_USIM_BWT_LSB_OFFSET 0
#define BSP_UICC_PHY_LLIF_USIM_BWT_LSB_WIDTH 16
typedef SYS_UWORD16 BspUicc_Usim_llif_UsimBwtLsb;
/****** Definitions for USIM_BWT_MSB Register ********/
#define BSP_UICC_PHY_LLIF_USIM_BWT_MSB_OFFSET 0
#define BSP_UICC_PHY_LLIF_USIM_BWT_MSB_WIDTH 7
/****** Definitions for DEBUG_REG Register ********/
#define BSP_UICC_PHY_LLIF_DEBUG_RX_SM_OFFSET 6
#define BSP_UICC_PHY_LLIF_DEBUG_RX_SM_WIDTH 2
#define BSP_UICC_PHY_LLIF_DEBUG_TX_SM_OFFSET 4
#define BSP_UICC_PHY_LLIF_DEBUG_TX_SM_WIDTH 2
#define BSP_UICC_PHY_LLIF_DEBUG_MAIN_STATE_SM_OFFSET 0
#define BSP_UICC_PHY_LLIF_DEBUG_MAIN_STATE_SM_WIDTH 4
#define BSP_UICC_PHY_LLIF_DEBUG_REG_OFFSET 0
#define BSP_UICC_PHY_LLIF_DEBUG_REG_WIDTH 16
enum
{
BSP_UICC_PHY_LLIF_DEBUG_MAIN_STATE_NO_CONNECT = 0,
BSP_UICC_PHY_LLIF_DEBUG_MAIN_STATE_SVCC_ON = 1,
BSP_UICC_PHY_LLIF_DEBUG_MAIN_STATE_SIO_RX = 2,
BSP_UICC_PHY_LLIF_DEBUG_MAIN_STATE_SCLK_ON = 3,
BSP_UICC_PHY_LLIF_DEBUG_MAIN_STATE_WAIT_ATR_INT = 4,
BSP_UICC_PHY_LLIF_DEBUG_MAIN_STATE_SRST_ON = 5,
BSP_UICC_PHY_LLIF_DEBUG_MAIN_STATE_WAIT_ATR_EXT = 6,
BSP_UICC_PHY_LLIF_DEBUG_MAIN_STATE_CLOCK_STOP = 7,
BSP_UICC_PHY_LLIF_DEBUG_MAIN_STATE_CLOCK_RESTART = 8,
BSP_UICC_PHY_LLIF_DEBUG_MAIN_STATE_WARM_RESET = 9,
BSP_UICC_PHY_LLIF_DEBUG_MAIN_STATE_DECODE_TS = 10,
BSP_UICC_PHY_LLIF_DEBUG_MAIN_STATE_COMMUNICATION = 11,
BSP_UICC_PHY_LLIF_DEBUG_MAIN_STATE_SRST_OFF = 12,
BSP_UICC_PHY_LLIF_DEBUG_MAIN_STATE_SCLK_OFF = 13,
BSP_UICC_PHY_LLIF_DEBUG_MAIN_STATE_SIO_TX = 14,
BSP_UICC_PHY_LLIF_DEBUG_MAIN_STATE_TDSIM = 15
};
typedef SYS_UWORD16 BspUicc_Usim_llif_DebugMainState;
/****** Definitions for CONF_SAM1_DIV Register ********/
#define BSP_UICC_PHY_LLIF_SAM1_DIV_OFFSET 0
#define BSP_UICC_PHY_LLIF_SAM1_DIV_WIDTH 12
/****** Definitions for CONF4_REG Register ********/
#define BSP_UICC_PHY_LLIF_CONF_WAITI_OFFSET 0
#define BSP_UICC_PHY_LLIF_CONF_WAITI_WIDTH 13
#define BSP_UICC_PHY_LLIF_REG_CONF4_REG_OFFSET 0
#define BSP_UICC_PHY_LLIF_REG_CONF4_REG_WIDTH 16
/****** Definitions for ATR_CLK_PRD_NBS Register ********/
#define BSP_UICC_PHY_LLIF_CLK_NBR_B4_ATR_OFFSET 0
#define BSP_UICC_PHY_LLIF_CLK_NBR_B4_ATR_WIDTH 16
/****** Definitions for CONF_ETU_DIV Register ********/
#define BSP_UICC_PHY_LLIF_CONF_ETU_DIV_OFFSET 0
#define BSP_UICC_PHY_LLIF_CONF_ETU_DIV_WIDTH 16
#define BSP_UICC_PHY_LLIF_CONF_ETU_DIV_RESET_VAL 0x5CF
/****** Definitions for CONF5_REG Register ********/
#define BSP_UICC_PHY_LLIF_SOFT_NHARD_FIDI_PROG_OFFSET 8
#define BSP_UICC_PHY_LLIF_SOFT_NHARD_FIDI_PROG_WIDTH 1
#define BSP_UICC_PHY_LLIF_CONF_FI_PROG_OFFSET 4
#define BSP_UICC_PHY_LLIF_CONF_FI_PROG_WIDTH 4
#define BSP_UICC_PHY_LLIF_CONF_DI_PROG_OFFSET 0
#define BSP_UICC_PHY_LLIF_CONF_DI_PROG_WIDTH 4
#define BSP_UICC_PHY_LLIF_REG_CONF5_REG_OFFSET 0
#define BSP_UICC_PHY_LLIF_REG_CONF5_REG_WIDTH 16
#define BSP_UICC_PHY_LLIF_SOFT_NHARD_FIDI_PROG_HW 0
#define BSP_UICC_PHY_LLIF_SOFT_NHARD_FIDI_PROG_SW 1
/*=============================================================================
* Types
*/
/*=============================================================================
* Description:
* Type for a 16 bit Register
*/
typedef SYS_UWORD16 BspUicc_Usim_llif_Reg;
/*=============================================================================
* Utility Macros
*/
/*=============================================================================
* Description:
* Gets a value from a local (shadowed or in local memory) register.
*
* _name - the name of a field, without the trailing _OFFSET or _WIDTH
* _ptr - pointer to the register that the field is in.
*/
#define BSP_UICC_PHY_LLIF_GET_LOCAL( _name, \
_ptr ) \
( \
BSPUTIL_BITUTIL_BIT_FIELD_GET( (_ptr), \
BSPUTIL_BITUTIL_DATAUNIT_16, \
_name ##_OFFSET, \
_name ##_WIDTH ) \
)
/*=============================================================================
* Description:
* Sets a value into a local (shadowed or in local memory) register field.
*
* _name - the name of a field, without the trailing _OFFSET or _WIDTH
* _ptr - pointer to the register that the field is in.
* _newValue - new value for the field.
*/
#define BSP_UICC_PHY_LLIF_SET_LOCAL( _name, \
_ptr, \
_newValue ) \
{ \
BSPUTIL_BITUTIL_BIT_FIELD_SET( (_ptr), \
(_newValue), \
BSPUTIL_BITUTIL_DATAUNIT_16, \
_name ##_OFFSET, \
_name ##_WIDTH ); \
}
/*=============================================================================
* Description:
* Gets a value from a register field. (XXXNote, don't use this for
* registers that must also be shadowed).
*
* _name - the name of a field, without the trailing _OFFSET or _WIDTH
* _ptr - pointer to the register that the field is in.
*/
#define BSP_UICC_PHY_LLIF_GET( _name, \
_ptr ) \
( \
BSPUTIL_BITUTIL_BIT_FIELD_GET( (_ptr), \
BSPUTIL_BITUTIL_DATAUNIT_16, \
_name ##_OFFSET, \
_name ##_WIDTH ) \
)
/*=============================================================================
* Description:
* Sets a value into a register field. (XXXNote, don't use this for
* registers that must also be shadowed).
*
* _name - the name of a field, without the trailing _OFFSET or _WIDTH
* _ptr - pointer to the register that the field is in.
* _newValue - new value for the field.
*/
#define BSP_UICC_PHY_LLIF_SET( _name, \
_ptr, \
_newValue ) \
{ \
BSPUTIL_BITUTIL_BIT_FIELD_SET( (_ptr), \
(_newValue), \
BSPUTIL_BITUTIL_DATAUNIT_16, \
_name ##_OFFSET, \
_name ##_WIDTH ); \
}
#endif
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