bspuicc_phy_llif.h

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/*===================================================================
 *    Copyright 2001-2002 Texas Instruments Inc. All rights reserved.
 */
#ifndef BSP_UICC_PHY_LLIF_HEADER
#define BSP_UICC_PHY_LLIF_HEADER

#include "bspUtil_BitUtil.h"
//#include "bspUtil_MemUtil.h"

/*=============================================================================
 * Component Description:
 *   Defines coponents and macros for the BSP_UICC Device Driver Block.
 */

/*=============================================================================
 * Constants
 */

/****** Definitions for USIM_CMD Register *******/
#define    BSP_UICC_PHY_LLIF_CMDIFRST_OFFSET          0
#define    BSP_UICC_PHY_LLIF_CMDIFRST_WIDTH           1

#define    BSP_UICC_PHY_LLIF_CMDSTOP_OFFSET           1
#define    BSP_UICC_PHY_LLIF_CMDSTOP_WIDTH            1

#define    BSP_UICC_PHY_LLIF_CMDSTART_OFFSET          2
#define    BSP_UICC_PHY_LLIF_CMDSTART_WIDTH           1

#define    BSP_UICC_PHY_LLIF_MODULE_CLK_EN_OFFSET     3
#define    BSP_UICC_PHY_LLIF_MODULE_CLK_EN_WIDTH      1

#define    BSP_UICC_PHY_LLIF_WARM_RESET_CMD_OFFSET    4
#define    BSP_UICC_PHY_LLIF_WARM_RESET_CMD_WIDTH     1

#define    BSP_UICC_PHY_LLIF_CLOCK_STOP_CMD_OFFSET    5
#define    BSP_UICC_PHY_LLIF_CLOCK_STOP_CMD_WIDTH     1

#define    BSP_UICC_PHY_LLIF_STP_EMV_ATR_TIMER_OFFSET 6
#define    BSP_UICC_PHY_LLIF_STP_EMV_ATR_TIMER_WIDTH  1

#define    BSP_UICC_PHY_LLIF_REG_USIM_CMD_OFFSET      0
#define    BSP_UICC_PHY_LLIF_REG_USIM_CMD_WIDTH      16

#define    BSP_UICC_PHY_LLIF_REG_USIM_CMD_CLEAR_ALL   0

enum
{
    BSP_UICC_PHY_LLIF_CMDIFRST_DISABLE   = 0,
    BSP_UICC_PHY_LLIF_CMDIFRST_ENABLE    = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_CmdIfReset;


enum
{
    BSP_UICC_PHY_LLIF_CMDSTOP_DISABLE    = 0,
    BSP_UICC_PHY_LLIF_CMDSTOP_ENABLE     = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_CmdStop;

enum
{
    BSP_UICC_PHY_LLIF_CMDSTART_DISABLE   = 0,
    BSP_UICC_PHY_LLIF_CMDSTART_ENABLE    = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_CmdStart;

enum
{
    BSP_UICC_PHY_LLIF_MODULE_CLK_DISABLE = 0,
    BSP_UICC_PHY_LLIF_MODULE_CLK_ENABLE  = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_ModuleClk;

enum
{
    BSP_UICC_PHY_LLIF_WARM_RESET_DISABLE = 0,
    BSP_UICC_PHY_LLIF_WARM_RESET_ENABLE  = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_WarmReset;

    
    

/****** Definitions for USIM_STAT Register *******/
#define    BSP_UICC_PHY_LLIF_STATNOCARD_OFFSET        0
#define    BSP_UICC_PHY_LLIF_STATNOCARD_WIDTH         1

#define    BSP_UICC_PHY_LLIF_STATTXPAR_OFFSET         1
#define    BSP_UICC_PHY_LLIF_STATTXPAR_WIDTH          1

#define    BSP_UICC_PHY_LLIF_STATLRC_OFFSET           2
#define    BSP_UICC_PHY_LLIF_STATLRC_WIDTH            1

#define    BSP_UICC_PHY_LLIF_CONFCODCONV_OFFSET       3
#define    BSP_UICC_PHY_LLIF_CONFCODCONV_WIDTH        1

#define    BSP_UICC_PHY_LLIF_X_MODE_OFFSET            4
#define    BSP_UICC_PHY_LLIF_X_MODE_WIDTH             1

#define    BSP_UICC_PHY_LLIF_REG_USIM_STAT_OFFSET     0
#define    BSP_UICC_PHY_LLIF_REG_USIM_STAT_WIDTH     16

enum
{
    BSP_UICC_PHY_LLIF_STATNOCARD_ABSENT  = 0,
    BSP_UICC_PHY_LLIF_STATNOCARD_PRESENT = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_StatNoCard;

enum
{
    BSP_UICC_PHY_LLIF_STATTXPAR_ERROR    = 0,
    BSP_UICC_PHY_LLIF_STATTXPAR_OK       = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_StatTxPar;

enum
{
    BSP_UICC_PHY_LLIF_STATLRC_OK         = 0,
    BSP_UICC_PHY_LLIF_STATLRC_ERROR      = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_StatLRC;

enum
{
    BSP_UICC_PHY_LLIF_CONFCODCONV_DIRECT = 0,
    BSP_UICC_PHY_LLIF_CONFCODCONV_INVERSE= 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_ConfCodConv;

/****** Definitions for USIM_CONF1 Register *******/
#define    BSP_UICC_PHY_LLIF_CONFSCLKLEV_OFFSET       0
#define    BSP_UICC_PHY_LLIF_CONFSCLKLEV_WIDTH        1

#define    BSP_UICC_PHY_LLIF_CONFSIOLOW_OFFSET        1
#define    BSP_UICC_PHY_LLIF_CONFSIOLOW_WIDTH         1

#define    BSP_UICC_PHY_LLIF_CONFBYPASS_OFFSET        2
#define    BSP_UICC_PHY_LLIF_CONFBYPASS_WIDTH         1

#define    BSP_UICC_PHY_LLIF_CONFSVCCLEV_OFFSET       3
#define    BSP_UICC_PHY_LLIF_CONFSVCCLEV_WIDTH        1

#define    BSP_UICC_PHY_LLIF_CONFSRSTLEV_OFFSET       4
#define    BSP_UICC_PHY_LLIF_CONFSRSTLEV_WIDTH        1

#define    BSP_UICC_PHY_LLIF_CONF_SCLK_EN_OFFSET      5
#define    BSP_UICC_PHY_LLIF_CONF_SCLK_EN_WIDTH       1

#define    BSP_UICC_PHY_LLIF_EMV_CONF_OFFSET          6
#define    BSP_UICC_PHY_LLIF_EMV_CONF_WIDTH           1

#define    BSP_UICC_PHY_LLIF_REG_USIM_CONF1_OFFSET    0
#define    BSP_UICC_PHY_LLIF_REG_USIM_CONF1_WIDTH    16

enum
{
    BSP_UICC_PHY_LLIF_CONFSCLKLEV_LOW    = 0,
    BSP_UICC_PHY_LLIF_CONFSCLKLEV_HIGH   = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_ConfSclkLev;

enum
{
    BSP_UICC_PHY_LLIF_CONFSIOLOW_DISABLE = 0,
    BSP_UICC_PHY_LLIF_CONFSIOLOW_ENABLE  = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_ConfSioLow;
enum
{
    BSP_UICC_PHY_LLIF_CONFBYPASS_DISABLE = 0,
    BSP_UICC_PHY_LLIF_CONFBYPASS_ENABLE  = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_ConfBypass;
enum
{
    BSP_UICC_PHY_LLIF_CONFSVCCLEV_LOW    = 0,
    BSP_UICC_PHY_LLIF_CONFSVCCLEV_HIGH   = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_ConfSvccLev;

enum
{
    BSP_UICC_PHY_LLIF_CONFSRST_LOW       = 0,
    BSP_UICC_PHY_LLIF_CONFSRST_HIGH      = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_ConfSrst;

enum
{
    BSP_UICC_PHY_LLIF_CONFSCLK_DISABLE   = 0,
    BSP_UICC_PHY_LLIF_CONFSCLK_ENABLE    = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_ConfSclk;


/****** Definitions for USIM_CONF2 Register *******/
#define    BSP_UICC_PHY_LLIF_CONFCHKPAR_OFFSET        0
#define    BSP_UICC_PHY_LLIF_CONFCHKPAR_WIDTH         1

#define    BSP_UICC_PHY_LLIF_CONFTXNRX_OFFSET         1
#define    BSP_UICC_PHY_LLIF_CONFTXNRX_WIDTH          1

#define    BSP_UICC_PHY_LLIF_CONFSCLKDIV_OFFSET       2
#define    BSP_UICC_PHY_LLIF_CONFSCLKDIV_WIDTH        2

#define    BSP_UICC_PHY_LLIF_ATR_ASYN_BYPASS_OFFSET   4
#define    BSP_UICC_PHY_LLIF_ATR_ASYN_BYPASS_WIDTH    1

#define    BSP_UICC_PHY_LLIF_CON_PROTOCOL_OFFSET      5
#define    BSP_UICC_PHY_LLIF_CON_PROTOCOL_WIDTH       1

#define    BSP_UICC_PHY_LLIF_CONF_EDC_OFFSET          6
#define    BSP_UICC_PHY_LLIF_CONF_EDC_WIDTH           1

#define    BSP_UICC_PHY_LLIF_CONFLRCCHECK_OFFSET      7
#define    BSP_UICC_PHY_LLIF_CONFLRCCHECK_WIDTH       1

#define    BSP_UICC_PHY_LLIF_CONF_RESENT_OFFSET       8
#define    BSP_UICC_PHY_LLIF_CONF_RESENT_WIDTH        3

#define    BSP_UICC_PHY_LLIF_REG_USIM_CONF2_OFFSET    0
#define    BSP_UICC_PHY_LLIF_REG_USIM_CONF2_WIDTH    16

enum
{
    BSP_UICC_PHY_LLIF_CONFCHKPAR_DISABLE    = 0,
    BSP_UICC_PHY_LLIF_CONFCHKPAR_ENABLE     = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_ConfChkPar;

enum
{
    BSP_UICC_PHY_LLIF_CONFTXNRX_RX          = 0,
    BSP_UICC_PHY_LLIF_CONFTXNRX_TX          = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_ConfTxnRx;

enum
{
    BSP_UICC_PHY_LLIF_CONFETUPERIOD_8       = 0,  /* for 8 times 1/F sclk */
    BSP_UICC_PHY_LLIF_CONFETUPERIOD_372     = 1,
    BSP_UICC_PHY_LLIF_CONFETUPERIOD_512_8   = 2,
    BSP_UICC_PHY_LLIF_CONFETUPERIOD_512_16  = 3
};
typedef SYS_UWORD8 BspUicc_Usim_llif_ConfEtuPeriod;

enum
{
    BSP_UICC_PHY_LLIF_SCLKDIV_13_4          = 0, /* for 13/4 MHz */
    BSP_UICC_PHY_LLIF_SCLKDIV_13_8          = 1  /* for 13/8 MHz */
};
typedef SYS_UWORD8 BspUicc_Usim_llif_SclkDiv;
enum
{
    BSP_UICC_PHY_LLIF_CONFPROTOCOL_T0       = 0,
    BSP_UICC_PHY_LLIF_CONFPROTOCOL_T1       = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_ConfProtocol;
enum
{
    BSP_UICC_PHY_LLIF_CONFEDC_LRC            = 0,
    BSP_UICC_PHY_LLIF_CONFEDC_CRC            = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_ConfEdc;
enum
{
    BSP_UICC_PHY_LLIF_CONFLRCCHECK_DISABLE   = 0,
    BSP_UICC_PHY_LLIF_CONFLRCCHECK_ENABLE    = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_ConfLrcCheck;

enum
{
    BSP_UICC_PHY_LLIF_CONFRESENT_DEF_VAL   = 0x7
};
typedef SYS_UWORD8 BspUicc_Usim_llif_ConfResent;

enum
{
    BSP_UICC_PHY_LLIF_ATR_ASYN_BYPASS_DISABLE= 0,
    BSP_UICC_PHY_LLIF_ATR_ASYN_BYPASS_ENABLE = 1
};
typedef SYS_UWORD8 BspUicc_Usim_llif_AtrAsynBypass;

/****** Definitions for USIM_CONF3 Register ********/
#define    BSP_UICC_PHY_LLIF_CONFTFUSIM_OFFSET             0
#define    BSP_UICC_PHY_LLIF_CONFTFUSIM_WIDTH              4

#define    BSP_UICC_PHY_LLIF_CONFTDUSIM_OFFSET             4
#define    BSP_UICC_PHY_LLIF_CONFTDUSIM_WIDTH              4

#define    BSP_UICC_PHY_LLIF_REG_USIM_CONF3_OFFSET         0
#define    BSP_UICC_PHY_LLIF_REG_USIM_CONF3_WIDTH         16

typedef SYS_UWORD8 BspUicc_Usim_llif_ConfWaiti;
typedef SYS_UWORD8 BspUicc_Usim_llif_ConfTdUsim;
typedef SYS_UWORD8 BspUicc_Usim_llif_ConfTfUsim;

/****** Definitions for USIM_IT Register ***********/
#define    BSP_UICC_PHY_LLIF_USIM_NATR_OFFSET              0
#define    BSP_UICC_PHY_LLIF_USIM_NATR_WIDTH               1

#define    BSP_UICC_PHY_LLIF_USIM_WT_OFFSET                1
#define    BSP_UICC_PHY_LLIF_USIM_WT_WIDTH                 1

#define    BSP_UICC_PHY_LLIF_USIM_OV_OFFSET                2
#define    BSP_UICC_PHY_LLIF_USIM_OV_WIDTH                 1

#define    BSP_UICC_PHY_LLIF_USIM_TX_OFFSET                3
#define    BSP_UICC_PHY_LLIF_USIM_TX_WIDTH                 1

#define    BSP_UICC_PHY_LLIF_USIM_RX_OFFSET                4
#define    BSP_UICC_PHY_LLIF_USIM_RX_WIDTH                 1

#define    BSP_UICC_PHY_LLIF_USIM_CD_OFFSET                5
#define    BSP_UICC_PHY_LLIF_USIM_CD_WIDTH                 1

#define    BSP_UICC_PHY_LLIF_USIM_EOB_OFFSET               6
#define    BSP_UICC_PHY_LLIF_USIM_EOB_WIDTH                1

#define    BSP_UICC_PHY_LLIF_USIM_TOC_OFFSET               7
#define    BSP_UICC_PHY_LLIF_USIM_TOC_WIDTH                1

#define    BSP_UICC_PHY_LLIF_USIM_TOB_OFFSET               8
#define    BSP_UICC_PHY_LLIF_USIM_TOB_WIDTH                1

#define    BSP_UICC_PHY_LLIF_USIM_RESENT_OFFSET            9
#define    BSP_UICC_PHY_LLIF_USIM_RESENT_WIDTH             1

#define    BSP_UICC_PHY_LLIF_USIM_TS_ERROR_OFFSET         10
#define    BSP_UICC_PHY_LLIF_USIM_TS_ERROR_WIDTH           1

#define    BSP_UICC_PHY_LLIF_EMV_ATR_LEN_TO_OFFSET        11
#define    BSP_UICC_PHY_LLIF_EMV_ATR_LEN_TO_WIDTH          1

#define    BSP_UICC_PHY_LLIF_REG_USIM_IT_OFFSET            0
#define    BSP_UICC_PHY_LLIF_REG_USIM_IT_WIDTH            16

#define    BSP_UICC_PHY_LLIF_INTERRUPT_CLEAR_ALL      0xFFFF
#define    BSP_UICC_PHY_LLIF_INTERRUPT_CLEAR               0

/****** Definitions for USIM_MASKIT Register *******/
#define    BSP_UICC_PHY_LLIF_MASK_USIM_NATR_OFFSET         0
#define    BSP_UICC_PHY_LLIF_MASK_USIM_NATR_WIDTH          1

#define    BSP_UICC_PHY_LLIF_MASK_USIM_WT_OFFSET           1