📄 lcd.h
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/*
+-----------------------------------------------------------------------------
| Project : ETM-Lite
| Modul : LCD
+-----------------------------------------------------------------------------
| Copyright 2002 Texas Instruments Berlin, AG
| All rights reserved.
|
| This file is confidential and a trade secret of Texas
| Instruments Berlin, AG
| The receipt of or possession of this file does not convey
| any rights to reproduce or disclose its contents or to
| manufacture, use, or sell anything it may describe, in
| whole, or in part, without the specific written consent of
| Texas Instruments Berlin, AG.
+-----------------------------------------------------------------------------
| Purpose :
|
+-----------------------------------------------------------------------------
*/
#ifndef LCD_H
#define LCD_H
#ifdef FPGA_PROT
#include "map_fpga.h"
#define LCD_INTERFACE_BASE_ADDR MAP_FPGA_LCD
#else
#endif
// Command Functions:
#define LCD_DISON 0xAF
#define LCD_DISOFF 0xAE
#define LCD_DISNOR 0xA6
#define LCD_DISINV 0xA7
#define LCD_DISCTL 0xCA
#define LCD_GCP64 0xCB
#define LCD_GCP16 0xCC
#define LCD_GSSET 0xCD
#define LCD_SLPIN 0x95
#define LCD_SLPOUT 0x94
#define LCD_SD_PSET 0x75
#define LCD_MD_PSET 0x76
#define LCD_SD_CSET 0x15
#define LCD_MD_CSET 0x16
#define LCD_DATCTL 0xBC
#define LCD_RAMWR 0x5C
#define LCD_RAMRD 0x5D
#define LCD_PTLIN 0xA8
#define LCD_PTLOUT 0xA9
#define LCD_ASCSET 0xAA
#define LCD_SCSTART 0xAB
#define LCD_VOLCTL 0xC6
#define LCD_NOP 0x25
#define LCD_OSCISEL 0x7
#define LCD_3500KSET 0xD1
#define LCD_3500KEND 0xD2
#define LCD_14MSET 0xD3
#define LCD_14MEND 0xD4
#define INIT_3500KSET 0x45
#define INIT_14MSET 0x4B
#define INIT_DATCTL 0x28 /* 5.6.5 bits for D-Sample */
#define INIT_OSCISEL 0x05
#define INIT_VOLCTL 0x7F /* Nominel "volume" */
#define INIT_VOLCTL_Ton 0x98 /* Activate power-IC timer */
#define INIT_GSSET 0x00
//******************************************************************************
// CLO
#define LCD_INTERFACE_BASE_ADDR 0xFFFFA000 // LCD interface on LOCOSTO !!
#define REG16(_addr) (*(volatile unsigned short *)(_addr))
//Register Offset
//---------------
#define LCD_INTERFACE_CNTL_REG_OFFSET 0x00
#define LCD_INTERFACE_LCD_CNTL_REG_OFFSET 0x02
#define LCD_INTERFACE_LCD_IF_STS_REG_OFFSET 0x04
#define LCD_INTERFACE_WR_FIFO_OFFSET 0x06
#define LCD_INTERFACE_RD_REG_OFFSET 0x08
//LCD_INTERFACE_CNTL_REG
//----------------------
#define LCD_INTERFACE_CNTL_REG REG16(LCD_INTERFACE_BASE_ADDR+LCD_INTERFACE_CNTL_REG_OFFSET)
#define LCD_INTERFACE_LCD_CNTL_REG REG16(LCD_INTERFACE_BASE_ADDR+LCD_INTERFACE_LCD_CNTL_REG_OFFSET)
#define SDRAM_IMAGE 1
#define IMIF_IMAGE 2
//#define FRAME_BUFFER_SDRAM_ADDRESS 0x10600000 //Located in the 6th MB of the 32MB availble (after ETM-Lite code and before the GSM code)
//#define FRAME_BUFFER_IMIF_ADDRESS 0x20000000 //Located in internal RAM
#define DMA_NUMBER_OF_CHANNEL 9
// Debug latch
#define DEBUG_LATCH (*(volatile unsigned short*)0x2400000) // D-Sample & E-Sample
#define DEBUG_LATCH_HI (*(volatile unsigned char*)0x2400001) // D-Sample & E-Sample
#define DEBUG_LATCH_LO (*(volatile unsigned char*)0x2400000) // D-Sample & E-Sample
// Configuration latch
#define CTRL_MCLK_VPP (*(volatile unsigned char*)0x2780000) // control the 13/14MHz and DC-DC
typedef enum {
CLK_DIV_BY_1=0,
CLK_DIV_BY_2=1,
CLK_DIV_BY_4=2,
CLK_DIV_BY_8=3
} T_CKCTL_DIV;
#if 0
#define BIT unsigned int
typedef struct
{
BIT ChannelNumb:4;
//DMA_CSDP
//--------------------
BIT TypeSize:2;
BIT SrcPort:3;
BIT DestPort:3;
BIT SrcPack:1;
BIT DestPack:1;
BIT SrcBurst:2;
BIT DestBurst:2;
//DMA_CCR
//-----------------------
BIT SyncNumb:5;
BIT SyncPr:1;
BIT EventSync:1;//fs
BIT Priority:1;
BIT Enable:1;
BIT Autoinit:1;
BIT Repeat:1;
BIT Fifofush:1;
BIT SrcAddressMode:2;
BIT DestAddressMode:2;
//DMA_CICR
//----------------------
BIT TimeoutIntEnable:1;
BIT DropIntEnable:1;
BIT HalfFrameIntEnable:1;
BIT FrameIntEnable:1;
BIT LastFrameIntEnable:1;
BIT BlockIntEnable:1;
//DMA_CSCR
//----------------------
BIT TimeoutInt:1;
BIT DropInt:1;
BIT HalfFrameInt:1;
BIT FrameInt:1;
BIT LastFrameInt:1;
BIT BlockInt:1;
//DMA_CSSA L and U
//----------------------
UINT32 SrcAdd;
//DMA_CDSA L and U
//----------------------
UINT32 DestAdd;
//DMA_CEN
//----------------------
UINT16 EltNumber;
//DMA_CFN
//----------------------
UINT16 FrameNumber;
//DMA_CEI
//----------------------
UINT16 EltIndex;
//DMA_CFI
//----------------------
UINT16 FrameIndex;
//-------------------------------------------------------------------
//Patern use to prepare data to transfert (use for test only)
//------------------------------------------------------------
UINT16 Pattern;
}T_CHANNEL_DESCRIPTOR;
typedef struct
{
//DMA_LCD_CTRL
//--------------------
BIT FrameMode:1;
BIT FrameItIe:1;
BIT BusErrorItIe:1;
BIT Frame1ItCond:1;
BIT Frame2ItCond:1;
BIT BusErrorItCond:1;
BIT LcdSrc:1;
//DMA_LCD_TOP_F1
//-----------------------
UINT32 LcdTopF1;
//DMA_LCD_BOT_F1
//-----------------------
UINT32 LcdBotF1;
//DMA_LCD_TOP_F2
//-----------------------
UINT32 LcdTopF2;
//DMA_LCD_BOT_F2
//-----------------------
UINT32 LcdBotF2;
}T_LCD_CHANNEL_DESCRIPTOR;
typedef struct
{
//Global register
//--------------------
BIT Autogating_on:1;
BIT Free:1;
T_CHANNEL_DESCRIPTOR DmaChannel[DMA_NUMBER_OF_CHANNEL];
T_LCD_CHANNEL_DESCRIPTOR LcdChannel;
}T_DMA_SYSTEM_STRUCT ;
extern UINT8 PixelClockDiv;
#endif
/*=== Private function prototypes ============================================*/
void lcd_off(void);
void lcd_init(void);
void setupPinMuxLCD(void);
void setup_PixelclockFreq(void);
UINT16 lcdGetClockDivider(void);
void init_lcd_ctrl_registers(void);
void EPSON_MD_TFD_LCD_INIT(void);
void MPU_UWIRE_nCS(unsigned char nCS1);
void MPU_UWIRE_SEND(unsigned short DnC, unsigned short Data);
void displayOnOff(unsigned char onOff);
void write_image_1(UINT16 *ptr_dst);
void write_image_2(UINT16 *ptr_dst);
void write_image_3(UINT16 *ptr_dst);
void write_image_4(UINT16 *ptr_dst);
void write_image_5(UINT16 *ptr_dst);
void write_image_6(UINT16 *ptr_dst);
void enable_dma(UINT8 image_src);
void DMA_SetupSystemDma(BOOL WithOrWithoutFree );
void DMA_EnableLcdIntFlags(UINT32 FrameItIe, UINT32 BusErrorItIe);
void DMATEST_LcdConfigPort(UINT32 SrcPort, UINT32 AddTop1, UINT32 AddBot1, UINT32 AddTop2, UINT32 AddBot2);
void DMATEST_LcdFrameMode(UINT32 FrMode);
void DMA_SetupChannel(void);
void r2d_nop_delay(UINT32 ms);
extern const unsigned char INIT_DISCTL[11]; // 12
extern const unsigned char INIT_GCP64[126];
extern const unsigned char INIT_GCP16[15]; // 16
extern const unsigned char INIT_MD_PSET[4];
extern const unsigned char INIT_MD_CSET[4] ;
extern const unsigned char INIT_SD_PSET[4];
extern const unsigned char INIT_SD_CSET[4];
extern const unsigned char INIT_ASCSET[];
extern const unsigned char INIT_SCSTART[2];
void lcd_text_refresh(void);
void LCD_L2D2_Initialization(void);
// void LCD_L2D2_load_img(unsigned char *data,unsigned short stride);
void LCD_L2D2_load_img(unsigned char *data, unsigned short x_size, unsigned short y_size);
void LCD_L2D2_load_img2(unsigned char *data, unsigned short stride);
//******************************************************************************
//BEGIN INC GENERATION
//--------------------------------------
//Register Offset
//-------------------
#define LCD_INTERFACE_CNTL_REG_OFFSET 0x00
#define LCD_INTERFACE_LCD_CNTL_REG_OFFSET 0x02
#define LCD_INTERFACE_LCD_IF_STS_REG_OFFSET 0x04
#define LCD_INTERFACE_WR_FIFO_OFFSET 0x06
#define LCD_INTERFACE_RD_REG_OFFSET 0x08
//LCD_INTERFACE_CNTL_REG
//-------------------
#define LCD_INTERFACE_CNTL_REG REG16(LCD_INTERFACE_BASE_ADDR+LCD_INTERFACE_CNTL_REG_OFFSET)
#define LCD_INTERFACE_CNTL_REG_N_DUMMY_POS 14
#define LCD_INTERFACE_CNTL_REG_N_DUMMY_NUMB 2
#define LCD_INTERFACE_CNTL_REG_N_DUMMY_RES_VAL 0x1
//R/W
#define LCD_INTERFACE_CNTL_REG_MIN_FRAME_SIZE_POS 12
#define LCD_INTERFACE_CNTL_REG_MIN_FRAME_SIZE_NUMB 2
#define LCD_INTERFACE_CNTL_REG_MIN_FRAME_SIZE_RES_VAL 0x3
//R/W
#define LCD_INTERFACE_CNTL_REG_SUSPEND_EN_POS 11
#define LCD_INTERFACE_CNTL_REG_SUSPEND_EN_NUMB 1
#define LCD_INTERFACE_CNTL_REG_SUSPEND_EN_RES_VAL 0x1
//R/W
#define LCD_INTERFACE_CNTL_REG_FLIP_BYTES_POS 10
#define LCD_INTERFACE_CNTL_REG_FLIP_BYTES_NUMB 1
#define LCD_INTERFACE_CNTL_REG_FLIP_BYTES_RES_VAL 0x0
//R/W
#define LCD_INTERFACE_CNTL_REG_MODE_POS 9
#define LCD_INTERFACE_CNTL_REG_MODE_NUMB 1
#define LCD_INTERFACE_CNTL_REG_MODE_RES_VAL 0x0
//R/W
#define LCD_INTERFACE_CNTL_REG_DMA_EN_POS 8
#define LCD_INTERFACE_CNTL_REG_DMA_EN_NUMB 1
#define LCD_INTERFACE_CNTL_REG_DMA_EN_RES_VAL 0x0
//R/W
#define LCD_INTERFACE_CNTL_REG_LCD_READ_EVENT_IT_EN_POS 7
#define LCD_INTERFACE_CNTL_REG_LCD_READ_EVENT_IT_EN_NUMB 1
#define LCD_INTERFACE_CNTL_REG_LCD_READ_EVENT_IT_EN_RES_VAL 0x0
//R/W
#define LCD_INTERFACE_CNTL_REG_FIFO_EMPTY_IT_EN_POS 6
#define LCD_INTERFACE_CNTL_REG_FIFO_EMPTY_IT_EN_NUMB 1
#define LCD_INTERFACE_CNTL_REG_FIFO_EMPTY_IT_EN_RES_VAL 0x0
//R/W
#define LCD_INTERFACE_CNTL_REG_RX_CLOCK_DIV_POS 4
#define LCD_INTERFACE_CNTL_REG_RX_CLOCK_DIV_NUMB 2
#define LCD_INTERFACE_CNTL_REG_RX_CLOCK_DIV_RES_VAL 0x0
//R/W
#define LCD_INTERFACE_CNTL_REG_TX_CLOCK_DIV_POS 2
#define LCD_INTERFACE_CNTL_REG_TX_CLOCK_DIV_NUMB 2
#define LCD_INTERFACE_CNTL_REG_TX_CLOCK_DIV_RES_VAL 0x0
//R/W
#define LCD_INTERFACE_CNTL_REG_CLOCK13_EN_POS 1
#define LCD_INTERFACE_CNTL_REG_CLOCK13_EN_NUMB 1
#define LCD_INTERFACE_CNTL_REG_CLOCK13_EN_RES_VAL 0x0
//R/W
#define LCD_INTERFACE_CNTL_REG_SOFT_NRST_POS 0
#define LCD_INTERFACE_CNTL_REG_SOFT_NRST_NUMB 1
#define LCD_INTERFACE_CNTL_REG_SOFT_NRST_RES_VAL 0x1
//R/W
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