📄 modified_booth_cla.v
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//Multiplication parameter
`define n 8 //Operation bits
`define c `n/2
//Modified Booth Multiplier
module modified_booth_cla(pro, x, y);
output [`n+`n-1:0] pro;
input [`n-1:0] x, y;
reg [`n-1:0] tmpx, tmpy;
wire [`n:0] pp0, pp1, pp2, pp3;
wire [`c-1:0] mul, shift, twocom;
always@(x or y)
begin
if (y == 8'b1000_0000)
begin
tmpx = y; tmpy = x;
end
else
begin
tmpx = x; tmpy = y;
end
end
booth_encoder m1 (.mul(mul), .shift(shift), .twocom(twocom), .x(tmpx));
ppgenerator m2 (.pp0(pp0), .pp1(pp1), .pp2(pp2), .pp3(pp3), .x(tmpy), .mul(mul), .shift(shift), .twocom(twocom));
com_tree_CLA m3 (.sum(pro), .ppin0(pp0), .ppin1(pp1), .ppin2(pp2), .ppin3(pp3));
endmodule
//Booth Encoder
module booth_encoder(mul, shift, twocom, x);
input [`n-1:0]x;
output [`c-1:0]mul, shift, twocom;
reg [`c-1:0]mul, shift, twocom;
reg [`n:0]word;
integer i;
always@(x)
begin
word = {x,1'b0};
for(i=0; i<`c; i=i+1)
begin
mul[i] = word[i+i]^word[i+i+1];
shift[i] = word[i+i+2]?~(word[i+i]|word[i+i+1]):(word[i+i]&word[i+i+1]);
twocom[i] = word[i+i+2];
end
end
endmodule
//Partial Product Generator
module ppgenerator(pp0, pp1, pp2, pp3, x, mul, shift, twocom);
input [`c-1:0] mul, shift, twocom;
input [`n-1:0] x;
output [`n:0] pp0, pp1, pp2, pp3;
wire [`n:0] pp0, pp1, pp2, pp3;
reg [`n:0] pp [`c-1:0];
reg [2:0] code [`c-1:0];
reg [`n-1:0] tmp;
reg [`n:0] xshi, xtwo, zero, xorg, xmul;
integer i;
always@(x or mul or shift or twocom)
begin
tmp = ~x + 1'b1;
xshi = {~tmp[`n-1],tmp[`n-2:0],1'b0};
xtwo = {~tmp[`n-1],tmp};
zero = {1'b1, `n'b0};
xorg = {~x[`n-1], x};
xmul = {~x[`n-1],x[`n-2:0],1'b0};
for (i=0; i<`c; i=i+1)
code[i] = {twocom[i], shift[i], mul[i]};
end
my_mux m0(.out(pp0), .xshi(xshi), .xtwo(xtwo), .zero(zero), .xorg(xorg), .xmul(xmul), .sel(code[0]));
my_mux m1(.out(pp1), .xshi(xshi), .xtwo(xtwo), .zero(zero), .xorg(xorg), .xmul(xmul), .sel(code[1]));
my_mux m2(.out(pp2), .xshi(xshi), .xtwo(xtwo), .zero(zero), .xorg(xorg), .xmul(xmul), .sel(code[2]));
my_mux m3(.out(pp3), .xshi(xshi), .xtwo(xtwo), .zero(zero), .xorg(xorg), .xmul(xmul), .sel(code[3]));
endmodule
module my_mux(out, xshi, xtwo, zero, xorg, xmul, sel);
output [`n:0] out;
input [`n:0] xshi, xtwo, zero, xorg, xmul;
input [ 2:0] sel;
reg [`n:0] out;
always@(xshi or xtwo or zero or xorg or xmul or sel)
begin
case(sel)
3'b000, 3'b100: out = zero;
3'b001 : out = xorg;
3'b010 : out = xmul;
3'b101 : out = xtwo;
3'b110 : out = xshi;
default: out = 'b0;
endcase
end
endmodule
//Compression Tree - Carry Lookahead Adder
module com_tree_CLA(sum, ppin0, ppin1, ppin2, ppin3);
output [`n+`n-1:0] sum;
input [`n:0] ppin0, ppin1 ,ppin2, ppin3;
wire [8:0] first_sum [1:0];
wire [11:0] second_sum;
wire [3:0] carry;
wire [8:0] tmp_pp [1:0];
wire [11:0] sum_fir_pp0, sum_fir_pp1;
wire [11:0] tmp_pp2;
wire [15:0] sum_sec_pp, sign;
//First operation
assign tmp_pp[0] = {2'b00, ppin0[`n:2]},
tmp_pp[1] = {2'b00, ppin2[`n:2]};
my_CLA_9bits add1 (.sum(first_sum[0]), .cout(carry[0]), .x(tmp_pp[0]), .y(ppin1), .cin(1'b0));
my_CLA_9bits add2 (.sum(first_sum[1]), .cout(carry[1]), .x(tmp_pp[1]), .y(ppin3), .cin(1'b0));
assign sum_fir_pp0 = {carry[0], first_sum[0], ppin0[1:0]},
sum_fir_pp1 = {carry[1], first_sum[1], ppin2[1:0]};
//Second operation
assign tmp_pp2 = {4'b0000, sum_fir_pp0[11:4]};
my_CLA_12bits add3 (.sum(second_sum), .cout(carry[2]), .x(tmp_pp2), .y(sum_fir_pp1), .cin(1'b0));
assign sum_sec_pp = {second_sum, sum_fir_pp0[3:0]};
//Final adder operation
assign sign = 16'hAB00;
my_CLA_16bits add4 (.sum(sum), .cout(carry[3]), .x(sign), .y(sum_sec_pp), .cin(1'b0));
endmodule
//First compression tree - 9_bits CLA
module my_CLA_9bits(sum, cout, x, y, cin);
parameter n = 9;
output [n-1:0] sum;
output cout;
input [n-1:0] x, y;
input cin;
reg [n-1:0] sum;
reg cout;
reg [n-1:0] p, g;
reg [n-1:1] c;
integer i;
always@(x or y or cin)
begin
g = x & y;
p = x ^ y;
c[1] = g[0] | (p[0] & cin);
for (i=1; i<n-1; i=i+1)
begin
c[i+1] = g[i] | (p[i] & c[i]);
end
cout = g[n-1] | (p[n-1] & c[n-1]);
sum[0] = p[0] ^ cin;
sum[n-1:1] = p[n-1:1] ^ c[n-1:1];
end
endmodule
//Second compression tree - 12_bits CLA
module my_CLA_12bits(sum, cout, x, y, cin);
parameter n = 12;
output [n-1:0] sum;
output cout;
input [n-1:0] x, y;
input cin;
reg [n-1:0] sum;
reg cout;
reg [n-1:0] p, g;
reg [n-1:1] c;
integer i;
always@(x or y or cin)
begin
g = x & y;
p = x ^ y;
c[1] = g[0] | (p[0] & cin);
for (i=1; i<n-1; i=i+1)
begin
c[i+1] = g[i] | (p[i] & c[i]);
end
cout = g[n-1] | (p[n-1] & c[n-1]);
sum[0] = p[0] ^ cin;
sum[n-1:1] = p[n-1:1] ^ c[n-1:1];
end
endmodule
//Final Adder - 16_bits CLA
module my_CLA_16bits(sum, cout, x, y, cin);
parameter n = 16;
output [n-1:0] sum;
output cout;
input [n-1:0] x, y;
input cin;
reg [n-1:0] sum;
reg cout;
reg [n-1:0] p, g;
reg [n-1:1] c;
integer i;
always@(x or y or cin)
begin
g = x & y;
p = x ^ y;
c[1] = g[0] | (p[0] & cin);
for (i=1; i<n-1; i=i+1)
begin
c[i+1] = g[i] | (p[i] & c[i]);
end
cout = g[n-1] | (p[n-1] & c[n-1]);
sum[0] = p[0] ^ cin;
sum[n-1:1] = p[n-1:1] ^ c[n-1:1];
end
endmodule
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