uart.map.eqn

基于MAXII的RS232串口通信程序.还有使用VB编写的上位机串口通信软件。

--K1_safe_q[20] is clk_div:inst1|lpm_counter:cnt_rtl_1|cntr_b67:auto_generated|safe_q[20]
--operation mode is arithmetic

K1_safe_q[20]_carry_eqn = K1L04;
K1_safe_q[20]_lut_out = K1_safe_q[20] $ (!K1_safe_q[20]_carry_eqn);
K1_safe_q[20] = DFFEAS(K1_safe_q[20]_lut_out, clk, !C1L1, , , , , , );

--K1L24 is clk_div:inst1|lpm_counter:cnt_rtl_1|cntr_b67:auto_generated|counter_cella20~COUT
--operation mode is arithmetic

K1L24 = CARRY(K1_safe_q[20] & !K1L04);


--K1_safe_q[21] is clk_div:inst1|lpm_counter:cnt_rtl_1|cntr_b67:auto_generated|safe_q[21]
--operation mode is arithmetic

K1_safe_q[21]_carry_eqn = K1L24;
K1_safe_q[21]_lut_out = K1_safe_q[21] $ (K1_safe_q[21]_carry_eqn);
K1_safe_q[21] = DFFEAS(K1_safe_q[21]_lut_out, clk, !C1L1, , , , , , );

--K1L44 is clk_div:inst1|lpm_counter:cnt_rtl_1|cntr_b67:auto_generated|counter_cella21~COUT
--operation mode is arithmetic

K1L44 = CARRY(!K1L24 # !K1_safe_q[21]);


--K1_safe_q[22] is clk_div:inst1|lpm_counter:cnt_rtl_1|cntr_b67:auto_generated|safe_q[22]
--operation mode is arithmetic

K1_safe_q[22]_carry_eqn = K1L44;
K1_safe_q[22]_lut_out = K1_safe_q[22] $ (!K1_safe_q[22]_carry_eqn);
K1_safe_q[22] = DFFEAS(K1_safe_q[22]_lut_out, clk, !C1L1, , , , , , );

--K1L64 is clk_div:inst1|lpm_counter:cnt_rtl_1|cntr_b67:auto_generated|counter_cella22~COUT
--operation mode is arithmetic

K1L64 = CARRY(K1_safe_q[22] & !K1L44);


--K1_safe_q[23] is clk_div:inst1|lpm_counter:cnt_rtl_1|cntr_b67:auto_generated|safe_q[23]
--operation mode is normal

K1_safe_q[23]_carry_eqn = K1L64;
K1_safe_q[23]_lut_out = K1_safe_q[23] $ (K1_safe_q[23]_carry_eqn);
K1_safe_q[23] = DFFEAS(K1_safe_q[23]_lut_out, clk, !C1L1, , , , , , );


--C1L8 is clk_div:inst1|reduce_nor~197
--operation mode is normal

C1L8 = K1_safe_q[20] & K1_safe_q[21] & K1_safe_q[22] & K1_safe_q[23];


--C1L1 is clk_div:inst1|reduce_nor~0
--operation mode is normal

C1L1 = C1L6 & C1L7 & C1L8;


--F1_RDR[4] is uart:inst|uart_receiver:u2|RDR[4]
--operation mode is normal

F1_RDR[4]_lut_out = F1_RSR[4];
F1_RDR[4] = DFFEAS(F1_RDR[4]_lut_out, clk, rst_n, , F1L03, , , , );


--F1_RDR[5] is uart:inst|uart_receiver:u2|RDR[5]
--operation mode is normal

F1_RDR[5]_lut_out = !F1_RSR[5];
F1_RDR[5] = DFFEAS(F1_RDR[5]_lut_out, clk, rst_n, , F1L03, , , , );


--F1_RDR[1] is uart:inst|uart_receiver:u2|RDR[1]
--operation mode is normal

F1_RDR[1]_lut_out = !F1_RSR[1];
F1_RDR[1] = DFFEAS(F1_RDR[1]_lut_out, clk, rst_n, , F1L03, , , , );


--F1_RDR[6] is uart:inst|uart_receiver:u2|RDR[6]
--operation mode is normal

F1_RDR[6]_lut_out = F1_RSR[6];
F1_RDR[6] = DFFEAS(F1_RDR[6]_lut_out, clk, rst_n, , F1L03, , , , );


--F1_RDR[2] is uart:inst|uart_receiver:u2|RDR[2]
--operation mode is normal

F1_RDR[2]_lut_out = F1_RSR[2];
F1_RDR[2] = DFFEAS(F1_RDR[2]_lut_out, clk, rst_n, , F1L03, , , , );


--F1_RDR[7] is uart:inst|uart_receiver:u2|RDR[7]
--operation mode is normal

F1_RDR[7]_lut_out = F1_RSR[7];
F1_RDR[7] = DFFEAS(F1_RDR[7]_lut_out, clk, rst_n, , F1L03, , , , );


--F1_RDR[3] is uart:inst|uart_receiver:u2|RDR[3]
--operation mode is normal

F1_RDR[3]_lut_out = !F1_RSR[3];
F1_RDR[3] = DFFEAS(F1_RDR[3]_lut_out, clk, rst_n, , F1L03, , , , );


--E1_cnt1[3] is uart:inst|br_gen:u1|cnt1[3]
--operation mode is normal

E1_cnt1[3]_lut_out = E1L8 & E1L92 # !E1_cnt1[4];
E1_cnt1[3] = DFFEAS(E1_cnt1[3]_lut_out, clk, VCC, , , , , , );


--E1_cnt1[2] is uart:inst|br_gen:u1|cnt1[2]
--operation mode is normal

E1_cnt1[2]_lut_out = E1L6;
E1_cnt1[2] = DFFEAS(E1_cnt1[2]_lut_out, clk, VCC, , , , , , );


--E1_cnt1[0] is uart:inst|br_gen:u1|cnt1[0]
--operation mode is normal

E1_cnt1[0]_lut_out = E1L2;
E1_cnt1[0] = DFFEAS(E1_cnt1[0]_lut_out, clk, VCC, , , , , , );


--E1_cnt1[1] is uart:inst|br_gen:u1|cnt1[1]
--operation mode is normal

E1_cnt1[1]_lut_out = E1L4 & E1L92 # !E1_cnt1[4];
E1_cnt1[1] = DFFEAS(E1_cnt1[1]_lut_out, clk, VCC, , , , , , );


--E1L22 is uart:inst|br_gen:u1|cnt1[4]~185
--operation mode is normal

E1L22 = E1_cnt1[3] & E1_cnt1[2] & E1_cnt1[0] & !E1_cnt1[1];


--E1_cnt1[4] is uart:inst|br_gen:u1|cnt1[4]
--operation mode is normal

E1_cnt1[4]_lut_out = E1L01 & E1L92 # !E1_cnt1[4];
E1_cnt1[4] = DFFEAS(E1_cnt1[4]_lut_out, clk, VCC, , , , , , );


--E1L92 is uart:inst|br_gen:u1|reduce_nor~36
--operation mode is normal

E1L92 = E1_cnt1[2] # E1_cnt1[0] # !E1_cnt1[1] # !E1_cnt1[3];


--E1L82 is uart:inst|br_gen:u1|process0~0
--operation mode is normal

E1L82 = E1_cnt1[4] & !E1L92 # !E1_cnt1[4] & E1L22;


--F1L72 is uart:inst|uart_receiver:u2|nextstate.start_detected~165
--operation mode is normal

F1L72 = F1_state.start_detected & !F1_bclkx8_rising;


--F1L82 is uart:inst|uart_receiver:u2|nextstate.start_detected~166
--operation mode is normal

F1L82 = F1_state.start_detected & F1_ct1[2] # !F1_ct1[0] # !F1_ct1[1];


--F1_state.idle is uart:inst|uart_receiver:u2|state.idle
--operation mode is normal

F1_state.idle_lut_out = !F1L42 & F1_state.recv_data # F1L72 # !rxd;
F1_state.idle = DFFEAS(F1_state.idle_lut_out, clk, rst_n, , , , , , );


--F1L32 is uart:inst|uart_receiver:u2|inc2~4
--operation mode is normal

F1L32 = F1L92 & F1_state.recv_data & F1L54;


--G1_tsr[3] is uart:inst|uart_transmitter:u3|tsr[3]
--operation mode is normal

G1_tsr[3]_lut_out = G1L51 & !F1_RDR[2] # !G1L51 & G1_tsr[4];
G1_tsr[3] = DFFEAS(G1_tsr[3]_lut_out, clk, rst_n, , G1L52, , , , );


--F1_RSR[0] is uart:inst|uart_receiver:u2|RSR[0]
--operation mode is normal

F1_RSR[0]_lut_out = F1_RSR[1];
F1_RSR[0] = DFFEAS(F1_RSR[0]_lut_out, clk, VCC, , F1L84, , , , );


--F1_RSR[4] is uart:inst|uart_receiver:u2|RSR[4]
--operation mode is normal

F1_RSR[4]_lut_out = F1_RSR[5];
F1_RSR[4] = DFFEAS(F1_RSR[4]_lut_out, clk, VCC, , F1L84, , , , );


--F1_RSR[5] is uart:inst|uart_receiver:u2|RSR[5]
--operation mode is normal

F1_RSR[5]_lut_out = F1_RSR[6];
F1_RSR[5] = DFFEAS(F1_RSR[5]_lut_out, clk, VCC, , F1L84, , , , );


--F1_RSR[1] is uart:inst|uart_receiver:u2|RSR[1]
--operation mode is normal

F1_RSR[1]_lut_out = F1_RSR[2];
F1_RSR[1] = DFFEAS(F1_RSR[1]_lut_out, clk, VCC, , F1L84, , , , );


--F1_RSR[6] is uart:inst|uart_receiver:u2|RSR[6]
--operation mode is normal

F1_RSR[6]_lut_out = F1_RSR[7];
F1_RSR[6] = DFFEAS(F1_RSR[6]_lut_out, clk, VCC, , F1L84, , , , );


--F1_RSR[2] is uart:inst|uart_receiver:u2|RSR[2]
--operation mode is normal

F1_RSR[2]_lut_out = F1_RSR[3];
F1_RSR[2] = DFFEAS(F1_RSR[2]_lut_out, clk, VCC, , F1L84, , , , );


--F1_RSR[7] is uart:inst|uart_receiver:u2|RSR[7]
--operation mode is normal

F1_RSR[7]_lut_out = rxd;
F1_RSR[7] = DFFEAS(F1_RSR[7]_lut_out, clk, VCC, , F1L84, , , , );


--F1_RSR[3] is uart:inst|uart_receiver:u2|RSR[3]
--operation mode is normal

F1_RSR[3]_lut_out = F1_RSR[4];
F1_RSR[3] = DFFEAS(F1_RSR[3]_lut_out, clk, VCC, , F1L84, , , , );


--E1L8 is uart:inst|br_gen:u1|add~126
--operation mode is arithmetic

E1L8_carry_eqn = E1L7;
E1L8 = E1_cnt1[3] $ (E1L8_carry_eqn);

--E1L9 is uart:inst|br_gen:u1|add~126COUT
--operation mode is arithmetic

E1L9 = CARRY(!E1L7 # !E1_cnt1[3]);


--E1L6 is uart:inst|br_gen:u1|add~125
--operation mode is arithmetic

E1L6_carry_eqn = E1L5;
E1L6 = E1_cnt1[2] $ (!E1L6_carry_eqn);

--E1L7 is uart:inst|br_gen:u1|add~125COUT
--operation mode is arithmetic

E1L7 = CARRY(E1_cnt1[2] & !E1L5);


--E1L2 is uart:inst|br_gen:u1|add~123
--operation mode is arithmetic

E1L2 = !E1_cnt1[0];

--E1L3 is uart:inst|br_gen:u1|add~123COUT
--operation mode is arithmetic

E1L3 = CARRY(E1_cnt1[0]);


--E1L4 is uart:inst|br_gen:u1|add~124
--operation mode is arithmetic

E1L4_carry_eqn = E1L3;
E1L4 = E1_cnt1[1] $ (E1L4_carry_eqn);

--E1L5 is uart:inst|br_gen:u1|add~124COUT
--operation mode is arithmetic

E1L5 = CARRY(!E1L3 # !E1_cnt1[1]);


--E1L01 is uart:inst|br_gen:u1|add~127
--operation mode is normal

E1L01_carry_eqn = E1L9;
E1L01 = E1_cnt1[4] $ (!E1L01_carry_eqn);


--F1L42 is uart:inst|uart_receiver:u2|nextstate.idle~226
--operation mode is normal

F1L42 = F1L92 & F1_state.recv_data & !F1L54;


--G1_tsr[4] is uart:inst|uart_transmitter:u3|tsr[4]
--operation mode is normal

G1_tsr[4]_lut_out = G1L51 & F1_RDR[3] # !G1L51 & G1_tsr[5];
G1_tsr[4] = DFFEAS(G1_tsr[4]_lut_out, clk, rst_n, , G1L52, , , , );


--F1L84 is uart:inst|uart_receiver:u2|RSR[0]~7
--operation mode is normal

F1L84 = F1L92 & F1_state.recv_data & F1L54 & rst_n;


--G1_tsr[5] is uart:inst|uart_transmitter:u3|tsr[5]
--operation mode is normal

G1_tsr[5]_lut_out = G1L51 & !F1_RDR[4] # !G1L51 & G1_tsr[6];
G1_tsr[5] = DFFEAS(G1_tsr[5]_lut_out, clk, rst_n, , G1L52, , , , );


--G1_tsr[6] is uart:inst|uart_transmitter:u3|tsr[6]
--operation mode is normal

G1_tsr[6]_lut_out = G1L51 & F1_RDR[5] # !G1L51 & G1_tsr[7];
G1_tsr[6] = DFFEAS(G1_tsr[6]_lut_out, clk, rst_n, , G1L52, , , , );


--G1_tsr[7] is uart:inst|uart_transmitter:u3|tsr[7]
--operation mode is normal

G1_tsr[7]_lut_out = G1L51 & !F1_RDR[6] # !G1L51 & G1_tsr[8];
G1_tsr[7] = DFFEAS(G1_tsr[7]_lut_out, clk, rst_n, , G1L52, , , , );


--G1_tsr[8] is uart:inst|uart_transmitter:u3|tsr[8]
--operation mode is normal

G1_tsr[8]_lut_out = G1L51 & !F1_RDR[7] # !G1L51 & !G1L33 & G1_tsr[8];
G1_tsr[8] = DFFEAS(G1_tsr[8]_lut_out, clk, rst_n, , , , , , );


--G1L33 is uart:inst|uart_transmitter:u3|tsr~838
--operation mode is normal

G1L33 = G1L71 & G1_state.tdata & G1L61 & !G1_state.synch;


--G1L43 is uart:inst|uart_transmitter:u3|txd_doneH~1
--operation mode is normal

G1L43 = G1_bclk_dlayed # G1L71 # !G1_state.tdata # !E1_ctr3[2];


--F1L62 is uart:inst|uart_receiver:u2|nextstate.recv_data~189
--operation mode is normal

F1L62 = F1_state.start_detected & !rxd & F1_bclkx8_rising & F1L44;


--sel[0] is sel[0]
--operation mode is input

sel[0] = INPUT();


--sel[1] is sel[1]
--operation mode is input

sel[1] = INPUT();


--sel[2] is sel[2]
--operation mode is input

sel[2] = INPUT();


--rxd is rxd
--operation mode is input

rxd = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--rst_n is rst_n
--operation mode is input

rst_n = INPUT();


--txd_startH is txd_startH
--operation mode is input

txd_startH = INPUT();


--rxd_readyH is rxd_readyH
--operation mode is output

rxd_readyH = OUTPUT(F1_rxd_readyH);


--txd_doneH is txd_doneH
--operation mode is output

txd_doneH = OUTPUT(!G1L43);


--txd is txd
--operation mode is output

txd = OUTPUT(!G1_tsr[0]);


--dig4 is dig4
--operation mode is output

dig4 = OUTPUT(D1_com_mten);


--dig3 is dig3
--operation mode is output

dig3 = OUTPUT(D1_com_mone);


--dig2 is dig2
--operation mode is output

dig2 = OUTPUT(D1_com_sten);


--dig1 is dig1
--operation mode is output

dig1 = OUTPUT(D1_com_sone);


--seven_seg[7] is seven_seg[7]
--operation mode is output

seven_seg[7] = OUTPUT(GND);


--seven_seg[6] is seven_seg[6]
--operation mode is output

seven_seg[6] = OUTPUT(!D1L34);


--seven_seg[5] is seven_seg[5]
--operation mode is output

seven_seg[5] = OUTPUT(D1L24);


--seven_seg[4] is seven_seg[4]
--operation mode is output

seven_seg[4] = OUTPUT(D1L14);


--seven_seg[3] is seven_seg[3]
--operation mode is output

seven_seg[3] = OUTPUT(D1L04);


--seven_seg[2] is seven_seg[2]
--operation mode is output

seven_seg[2] = OUTPUT(D1L93);


--seven_seg[1] is seven_seg[1]
--operation mode is output

seven_seg[1] = OUTPUT(D1L83);


--seven_seg[0] is seven_seg[0]
--operation mode is output

seven_seg[0] = OUTPUT(D1L73);


--F1L33 is uart:inst|uart_receiver:u2|RDR[0]~32
--operation mode is normal

F1L33 = !F1_RDR[0];


--F1L53 is uart:inst|uart_receiver:u2|RDR[1]~33
--operation mode is normal

F1L53 = !F1_RDR[1];


--F1L83 is uart:inst|uart_receiver:u2|RDR[3]~34
--operation mode is normal

F1L83 = !F1_RDR[3];


--F1L14 is uart:inst|uart_receiver:u2|RDR[5]~35
--operation mode is normal

F1L14 = !F1_RDR[5];