📄 uart.map.rpt
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; state.synch ; 0 ; 1 ; 1 ;
; state.tdata ; 1 ; 0 ; 1 ;
+-------------+-------------+-------------+----------------------+
+----------------------------------------------------------------------------+
; State Machine - |uart_test|uart:inst|uart_receiver:u2|state ;
+----------------------+-----------------+----------------------+------------+
; Name ; state.recv_data ; state.start_detected ; state.idle ;
+----------------------+-----------------+----------------------+------------+
; state.idle ; 0 ; 0 ; 0 ;
; state.start_detected ; 0 ; 1 ; 1 ;
; state.recv_data ; 1 ; 0 ; 1 ;
+----------------------+-----------------+----------------------+------------+
+-----------+
; Hierarchy ;
+-----------+
uart_test
|-- uart:inst
|-- br_gen:u1
|-- lpm_counter:ctr2_rtl_0
|-- cntr_rm6:auto_generated
|-- uart_receiver:u2
|-- uart_transmitter:u3
|-- clk_div:inst1
|-- lpm_counter:cnt_rtl_1
|-- cntr_b67:auto_generated
|-- scan:inst6
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+---------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------------+
; |uart_test ; 183 (0) ; 114 ; 0 ; 22 ; 0 ; 69 (0) ; 50 (0) ; 64 (0) ; 45 (0) ; |uart_test ;
; |clk_div:inst1| ; 32 (8) ; 24 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 24 (0) ; 24 (0) ; |uart_test|clk_div:inst1 ;
; |lpm_counter:cnt_rtl_1| ; 24 (0) ; 24 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 24 (0) ; 24 (0) ; |uart_test|clk_div:inst1|lpm_counter:cnt_rtl_1 ;
; |cntr_b67:auto_generated| ; 24 (24) ; 24 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 24 (24) ; 24 (24) ; |uart_test|clk_div:inst1|lpm_counter:cnt_rtl_1|cntr_b67:auto_generated ;
; |scan:inst6| ; 37 (37) ; 26 ; 0 ; 0 ; 0 ; 11 (11) ; 18 (18) ; 8 (8) ; 0 (0) ; |uart_test|scan:inst6 ;
; |uart:inst| ; 114 (0) ; 64 ; 0 ; 0 ; 0 ; 50 (0) ; 32 (0) ; 32 (0) ; 21 (0) ; |uart_test|uart:inst ;
; |br_gen:u1| ; 31 (23) ; 17 ; 0 ; 0 ; 0 ; 14 (14) ; 6 (6) ; 11 (3) ; 13 (5) ; |uart_test|uart:inst|br_gen:u1 ;
; |lpm_counter:ctr2_rtl_0| ; 8 (0) ; 8 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (0) ; 8 (0) ; |uart_test|uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0 ;
; |cntr_rm6:auto_generated| ; 8 (8) ; 8 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; 8 (8) ; |uart_test|uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated ;
; |uart_receiver:u2| ; 52 (52) ; 28 ; 0 ; 0 ; 0 ; 24 (24) ; 21 (21) ; 7 (7) ; 4 (4) ; |uart_test|uart:inst|uart_receiver:u2 ;
; |uart_transmitter:u3| ; 31 (31) ; 19 ; 0 ; 0 ; 0 ; 12 (12) ; 5 (5) ; 14 (14) ; 4 (4) ; |uart_test|uart:inst|uart_transmitter:u3 ;
+---------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/Brent/Project/GFEC_MAXII_Kit/program/RS232/RS232/uart.map.eqn.
+-------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+--------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path ;
+----------------------------------+-----------------+--------------------------------------------------------------------------+
; br_gen.vhd ; yes ; D:/Brent/Project/GFEC_MAXII_Kit/program/RS232/RS232/br_gen.vhd ;
; uart.vhd ; yes ; D:/Brent/Project/GFEC_MAXII_Kit/program/RS232/RS232/uart.vhd ;
; uart_receiver.vhd ; yes ; D:/Brent/Project/GFEC_MAXII_Kit/program/RS232/RS232/uart_receiver.vhd ;
; uart_transmitter.vhd ; yes ; D:/Brent/Project/GFEC_MAXII_Kit/program/RS232/RS232/uart_transmitter.vhd ;
; uart_test.bdf ; yes ; D:/Brent/Project/GFEC_MAXII_Kit/program/RS232/RS232/uart_test.bdf ;
; clk_div.vhd ; yes ; D:/Brent/Project/GFEC_MAXII_Kit/program/RS232/RS232/clk_div.vhd ;
; scan.vhd ; yes ; D:/Brent/Project/GFEC_MAXII_Kit/program/RS232/RS232/scan.vhd ;
; lpm_counter.tdf ; yes ; c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf ;
; lpm_constant.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/lpm_constant.inc ;
; lpm_decode.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/lpm_decode.inc ;
; lpm_add_sub.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/lpm_add_sub.inc ;
; cmpconst.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/cmpconst.inc ;
; lpm_compare.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/lpm_compare.inc ;
; lpm_counter.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/lpm_counter.inc ;
; dffeea.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/dffeea.inc ;
; alt_synch_counter.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/alt_synch_counter.inc ;
; alt_synch_counter_f.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.inc ;
; alt_counter_stratix.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal42.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/aglobal42.inc ;
; db/cntr_rm6.tdf ; yes ; D:/Brent/Project/GFEC_MAXII_Kit/program/RS232/RS232/db/cntr_rm6.tdf ;
; db/cntr_b67.tdf ; yes ; D:/Brent/Project/GFEC_MAXII_Kit/program/RS232/RS232/db/cntr_b67.tdf ;
+----------------------------------+-----------------+--------------------------------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource ; Usage ;
+-----------------------------------+---------+
; Logic cells ; 183 ;
; Total combinational functions ; 133 ;
; Total 4-input functions ; 55 ;
; Total 3-input functions ; 20 ;
; Total 2-input functions ; 11 ;
; Total 1-input functions ; 47 ;
; Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 114 ;
; Total logic cells in carry chains ; 45 ;
; I/O pins ; 22 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 93 ;
; Total fan-out ; 703 ;
; Average fan-out ; 3.43 ;
+-----------------------------------+---------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.2 Build 157 12/07/2004 SJ Web Edition
Info: Processing started: Tue May 17 07:58:15 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off uart -c uart
Info: Found 2 design units, including 1 entities, in source file br_gen.vhd
Info: Found design unit 1: br_gen-arch
Info: Found entity 1: br_gen
Info: Found 2 design units, including 1 entities, in source file uart.vhd
Info: Found design unit 1: uart-a
Info: Found entity 1: uart
Info: Found 2 design units, including 1 entities, in source file uart_receiver.vhd
Info: Found design unit 1: uart_receiver-arch
Info: Found entity 1: uart_receiver
Info: Found 2 design units, including 1 entities, in source file uart_transmitter.vhd
Info: Found design unit 1: uart_transmitter-arch
Info: Found entity 1: uart_transmitter
Info: Found 1 design units, including 1 entities, in source file uart_test.bdf
Info: Found entity 1: uart_test
Info: Found 2 design units, including 1 entities, in source file clk_div.vhd
Info: Found design unit 1: clk_div-a
Info: Found entity 1: clk_div
Info: Found 2 design units, including 1 entities, in source file scan.vhd
Info: Found design unit 1: scan-arch
Info: Found entity 1: scan
Warning: VHDL Signal Declaration warning at br_gen.vhd(17): ignored default value for signal "ctr2"
Warning: VHDL Signal Declaration warning at br_gen.vhd(18): ignored default value for signal "ctr3"
Warning: VHDL Process Statement warning at scan.vhd(27): signal "rst" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at scan.vhd(28): signal "rxd_data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at scan.vhd(29): signal "rxd_data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: VHDL Case Statement information at scan.vhd(62): OTHERS choice is never selected
Info: VHDL Case Statement information at scan.vhd(87): OTHERS choice is never selected
Warning: VHDL Process Statement warning at clk_div.vhd(18): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: State machine "|uart_test|uart:inst|uart_transmitter:u3|state" contains 3 states and 0 state bits
Info: State machine "|uart_test|uart:inst|uart_receiver:u2|state" contains 3 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|uart_test|uart:inst|uart_transmitter:u3|state"
Info: Encoding result for state machine "|uart_test|uart:inst|uart_transmitter:u3|state"
Info: Completed encoding using 3 state bits
Info: Encoded state bit "uart:inst|uart_transmitter:u3|state.tdata"
Info: Encoded state bit "uart:inst|uart_transmitter:u3|state.synch"
Info: Encoded state bit "uart:inst|uart_transmitter:u3|state.idle"
Info: State "|uart_test|uart:inst|uart_transmitter:u3|state.idle" uses code string "000"
Info: State "|uart_test|uart:inst|uart_transmitter:u3|state.synch" uses code string "011"
Info: State "|uart_test|uart:inst|uart_transmitter:u3|state.tdata" uses code string "101"
Info: Selected Auto state machine encoding method for state machine "|uart_test|uart:inst|uart_receiver:u2|state"
Info: Encoding result for state machine "|uart_test|uart:inst|uart_receiver:u2|state"
Info: Completed encoding using 3 state bits
Info: Encoded state bit "uart:inst|uart_receiver:u2|state.recv_data"
Info: Encoded state bit "uart:inst|uart_receiver:u2|state.start_detected"
Info: Encoded state bit "uart:inst|uart_receiver:u2|state.idle"
Info: State "|uart_test|uart:inst|uart_receiver:u2|state.idle" uses code string "000"
Info: State "|uart_test|uart:inst|uart_receiver:u2|state.start_detected" uses code string "011"
Info: State "|uart_test|uart:inst|uart_receiver:u2|state.recv_data" uses code string "101"
Info: Inferred 2 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: "uart:inst|br_gen:u1|ctr2[0]~8"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=24) from the following logic: "clk_div:inst1|cnt[0]~24"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_rm6.tdf
Info: Found entity 1: cntr_rm6
Info: Found 1 design units, including 1 entities, in source file db/cntr_b67.tdf
Info: Found entity 1: cntr_b67
Warning: Output pins are stuck at VCC or GND
Warning: Pin "seven_seg[7]" stuck at GND
Info: Registers with preset signals will power-up high
Info: Implemented 205 device resources after synthesis - the final resource count might be different
Info: Implemented 7 input pins
Info: Implemented 15 output pins
Info: Implemented 183 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
Info: Processing ended: Tue May 17 07:58:18 2005
Info: Elapsed time: 00:00:03
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