📄 uart.fit.rpt
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; Global clocks ; 4 / 4 ( 100 % ) ;
; LAB clocks ; 12 / 72 ( 16 % ) ;
; LUT chains ; 12 / 1,143 ( 1 % ) ;
; Local interconnects ; 181 / 3,938 ( 4 % ) ;
; R4s ; 93 / 2,832 ( 3 % ) ;
+----------------------------+----------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 7.52) ; Number of LABs (Total = 23) ;
+--------------------------------------------+------------------------------+
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 3 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 3 ;
; 9 ; 2 ;
; 10 ; 10 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 2.04) ; Number of LABs (Total = 23) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 13 ;
; 1 Async. load ; 1 ;
; 1 Clock ; 19 ;
; 1 Clock enable ; 6 ;
; 2 Clock enables ; 5 ;
; 2 Clocks ; 3 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 7.83) ; Number of LABs (Total = 23) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 2 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 3 ;
; 9 ; 2 ;
; 10 ; 5 ;
; 11 ; 4 ;
; 12 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 4.52) ; Number of LABs (Total = 23) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 5 ;
; 2 ; 3 ;
; 3 ; 2 ;
; 4 ; 2 ;
; 5 ; 3 ;
; 6 ; 1 ;
; 7 ; 2 ;
; 8 ; 3 ;
; 9 ; 0 ;
; 10 ; 2 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 7.26) ; Number of LABs (Total = 23) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 3 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 3 ;
; 5 ; 2 ;
; 6 ; 2 ;
; 7 ; 0 ;
; 8 ; 3 ;
; 9 ; 1 ;
; 10 ; 2 ;
; 11 ; 1 ;
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 1 ;
; 15 ; 1 ;
; 16 ; 0 ;
; 17 ; 0 ;
; 18 ; 0 ;
; 19 ; 1 ;
+---------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.2 Build 157 12/07/2004 SJ Web Edition
Info: Processing started: Tue May 17 07:58:20 2005
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off uart -c uart
Info: Selected device EPM1270T144C5ES for design "uart"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM570T144C5 is compatible
Info: Device EPM1270T144C5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 18
Info: Automatically promoted some destinations of signal "clk_div:inst1|lpm_counter:cnt_rtl_1|cntr_b67:auto_generated|safe_q[13]" to use Global clock
Info: Destination "clk_div:inst1|lpm_counter:cnt_rtl_1|cntr_b67:auto_generated|counter_cella13" may be non-global or may not use global clock
Info: Destination "clk_div:i
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