uart.fit.rpt

基于MAXII的RS232串口通信程序.还有使用VB编写的上位机串口通信软件。

Fitter report for uart
Tue May 17 07:58:24 2005
Version 4.2 Build 157 12/07/2004 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Equations
  6. Pin-Out File
  7. Fitter Resource Usage Summary
  8. Input Pins
  9. Output Pins
 10. I/O Bank Usage
 11. All Package Pins
 12. Output Pin Default Load For Reported TCO
 13. Fitter Resource Utilization by Entity
 14. Delay Chain Summary
 15. Control Signals
 16. Global & Other Fast Signals
 17. Non-Global High Fan-Out Signals
 18. Interconnect Usage Summary
 19. LAB Logic Elements
 20. LAB-wide Signals
 21. LAB Signals Sourced
 22. LAB Signals Sourced Out
 23. LAB Distinct Inputs
 24. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+-----------------------------------------------------------------+
; Fitter Summary                                                  ;
+-----------------------+-----------------------------------------+
; Fitter Status         ; Successful - Tue May 17 07:58:24 2005   ;
; Quartus II Version    ; 4.2 Build 157 12/07/2004 SJ Web Edition ;
; Revision Name         ; uart                                    ;
; Top-level Entity Name ; uart_test                               ;
; Family                ; MAX II                                  ;
; Device                ; EPM1270T144C5ES                         ;
; Timing Models         ; Preliminary                             ;
; Total logic elements  ; 173 / 1,270 ( 13 % )                    ;
; Total pins            ; 22 / 116 ( 18 % )                       ;
; Total virtual pins    ; 0                                       ;
; UFM blocks            ; 0 / 1 ( 0 % )                           ;
+-----------------------+-----------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                 ;
+---------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                        ; Setting                        ; Default Value                  ;
+---------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                        ; EPM1270T144C5ES                ;                                ;
; Use smart compilation                                         ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                   ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                      ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                          ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                   ; Off                            ; Off                            ;
; Guarantee I/O paths have zero hold time at Fast Timing Corner ; On                             ; On                             ;
; Optimize Timing                                               ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                    ; On                             ; On                             ;
; Limit to One Fitting Attempt                                  ; Off                            ; Off                            ;
; Final Placement Optimizations                                 ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                 ; 1                              ; 1                              ;
; Slow Slew Rate                                                ; Off                            ; Off                            ;
; PCI I/O                                                       ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                         ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic            ; Off                            ; Off                            ;
; Perform Register Duplication                                  ; Off                            ; Off                            ;
; Perform Register Retiming                                     ; Off                            ; Off                            ;
; Fitter Effort                                                 ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                               ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                      ; Auto                           ; Auto                           ;
; Auto Register Duplication                                     ; Off                            ; Off                            ;
; Auto Global Clock                                             ; On                             ; On                             ;
; Auto Global Register Control Signals                          ; On                             ; On                             ;
; Always Enable Input Buffers                                   ; Off                            ; Off                            ;
+---------------------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Passive Serial           ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in D:/Brent/Project/GFEC_MAXII_Kit/program/RS232/RS232/uart.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/Brent/Project/GFEC_MAXII_Kit/program/RS232/RS232/uart.pin.