📄 seven_segment.vho

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💻 VHO
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-- pragma translate_on
PORT MAP (
	dataa => qout_a1_a_a135,
	datab => qout_a2_a_a136,
	datac => qout_a3_a_a137,
	datad => qout_a0_a_a134,
	combout => Mux_a169);

Mux_a170_I : cycloneii_lcell_comb
-- Equation(s):
-- Mux_a170 = qout_a1_a_a135 & (qout_a2_a_a136 & !qout_a3_a_a137 & qout_a0_a_a134 # !qout_a2_a_a136 & (qout_a0_a_a134 # !qout_a3_a_a137)) # !qout_a1_a_a135 & (qout_a2_a_a136 & qout_a3_a_a137 # !qout_a2_a_a136 & !qout_a3_a_a137 & qout_a0_a_a134)

-- pragma translate_off
GENERIC MAP (
	sum_lutc_input => "datac",
	lut_mask => "0110101101000010")
-- pragma translate_on
PORT MAP (
	dataa => qout_a1_a_a135,
	datab => qout_a2_a_a136,
	datac => qout_a3_a_a137,
	datad => qout_a0_a_a134,
	combout => Mux_a170);

Mux_a171_I : cycloneii_lcell_comb
-- Equation(s):
-- Mux_a171 = qout_a2_a_a136 & (qout_a3_a_a137 # !qout_a0_a_a134 # !qout_a1_a_a135) # !qout_a2_a_a136 & (qout_a1_a_a135 $ qout_a3_a_a137)

-- pragma translate_off
GENERIC MAP (
	sum_lutc_input => "datac",
	lut_mask => "1101011011011110")
-- pragma translate_on
PORT MAP (
	dataa => qout_a1_a_a135,
	datab => qout_a2_a_a136,
	datac => qout_a3_a_a137,
	datad => qout_a0_a_a134,
	combout => Mux_a171);

Mux_a172_I : cycloneii_lcell_comb
-- Equation(s):
-- Mux_a172 = !qout_a1_a_a135 & !qout_a2_a_a136 # !qout_a3_a_a137

-- pragma translate_off
GENERIC MAP (
	sum_lutc_input => "datac",
	lut_mask => "0001111100011111")
-- pragma translate_on
PORT MAP (
	dataa => qout_a1_a_a135,
	datab => qout_a2_a_a136,
	datac => qout_a3_a_a137,
	combout => Mux_a172);

hex0_a0_a_aI : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => Mux_a165,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_hex0(0));

hex0_a1_a_aI : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => Mux_a166,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_hex0(1));

hex0_a2_a_aI : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => Mux_a167,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_hex0(2));

hex0_a3_a_aI : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => Mux_a168,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_hex0(3));

hex0_a4_a_aI : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => Mux_a169,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_hex0(4));

hex0_a5_a_aI : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => Mux_a170,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_hex0(5));

hex0_a6_a_aI : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => ALT_INV_Mux_a171,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_hex0(6));

hex1_a0_a_aI : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => ALT_INV_Mux_a172,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_hex1(0));

hex1_a1_a_aI : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_hex1(1));

hex1_a2_a_aI : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_hex1(2));

hex1_a3_a_aI : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => ALT_INV_Mux_a172,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_hex1(3));

hex1_a4_a_aI : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => ALT_INV_Mux_a172,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_hex1(4));

hex1_a5_a_aI : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => ALT_INV_Mux_a172,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_hex1(5));

hex1_a6_a_aI : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_hex1(6));

modeout_aI : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => mode_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_modeout);
END structure;
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💿 文件大小 100 K
👤 上传用户 albert333
📂 所属分类单片机开发
🏷️ 相关标签

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