seven_segment.vho

以QuatusⅡ为平台

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.0 Build 148 04/26/2005 SJ Web Edition"

-- DATE "11/28/2007 15:34:31"

-- 
-- Device: Altera EP2C35F672C6 Package FBGA672
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cycloneii;
USE IEEE.std_logic_1164.all;
USE cycloneii.cycloneii_components.all;

ENTITY 	seven_segment IS
    PORT (
	mode : IN std_logic;
	reset : IN std_logic;
	clk : IN std_logic;
	hex0 : OUT std_logic_vector(6 DOWNTO 0);
	hex1 : OUT std_logic_vector(6 DOWNTO 0);
	modeout : OUT std_logic
	);
END seven_segment;

ARCHITECTURE structure OF seven_segment IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_mode : std_logic;
SIGNAL ww_reset : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_hex0 : std_logic_vector(6 DOWNTO 0);
SIGNAL ww_hex1 : std_logic_vector(6 DOWNTO 0);
SIGNAL ww_modeout : std_logic;
SIGNAL output_a5clkctrl_I_INCLK_bus : std_logic_vector(3 DOWNTO 0);
SIGNAL output_a4clkctrl_I_INCLK_bus : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a24_a_aclkctrl_I_INCLK_bus : std_logic_vector(3 DOWNTO 0);
SIGNAL clk_aclkctrl_I_INCLK_bus : std_logic_vector(3 DOWNTO 0);
SIGNAL a_acounter2_aoutput_a1_a : std_logic;
SIGNAL count1_a24_a : std_logic;
SIGNAL count1_a23_a : std_logic;
SIGNAL count1_a22_a : std_logic;
SIGNAL count1_a21_a : std_logic;
SIGNAL count1_a20_a : std_logic;
SIGNAL count1_a19_a : std_logic;
SIGNAL count1_a18_a : std_logic;
SIGNAL count1_a17_a : std_logic;
SIGNAL count1_a16_a : std_logic;
SIGNAL count1_a15_a : std_logic;
SIGNAL count1_a14_a : std_logic;
SIGNAL count1_a13_a : std_logic;
SIGNAL count1_a12_a : std_logic;
SIGNAL count1_a11_a : std_logic;
SIGNAL count1_a10_a : std_logic;
SIGNAL count1_a9_a : std_logic;
SIGNAL count1_a8_a : std_logic;
SIGNAL count1_a7_a : std_logic;
SIGNAL count1_a6_a : std_logic;
SIGNAL count1_a5_a : std_logic;
SIGNAL count1_a4_a : std_logic;
SIGNAL count1_a3_a : std_logic;
SIGNAL count1_a2_a : std_logic;
SIGNAL count1_a1_a : std_logic;
SIGNAL count1_a0_a : std_logic;
SIGNAL count1_a0_a_a255 : std_logic;
SIGNAL count1_a0_a_a254 : std_logic;
SIGNAL count1_a1_a_a257 : std_logic;
SIGNAL count1_a1_a_a256 : std_logic;
SIGNAL count1_a2_a_a259 : std_logic;
SIGNAL count1_a2_a_a258 : std_logic;
SIGNAL count1_a3_a_a261 : std_logic;
SIGNAL count1_a3_a_a260 : std_logic;
SIGNAL count1_a4_a_a263 : std_logic;
SIGNAL count1_a4_a_a262 : std_logic;
SIGNAL count1_a5_a_a265 : std_logic;
SIGNAL count1_a5_a_a264 : std_logic;
SIGNAL count1_a6_a_a267 : std_logic;
SIGNAL count1_a6_a_a266 : std_logic;
SIGNAL count1_a7_a_a269 : std_logic;
SIGNAL count1_a7_a_a268 : std_logic;
SIGNAL count1_a8_a_a271 : std_logic;
SIGNAL count1_a8_a_a270 : std_logic;
SIGNAL count1_a9_a_a273 : std_logic;
SIGNAL count1_a9_a_a272 : std_logic;
SIGNAL count1_a10_a_a275 : std_logic;
SIGNAL count1_a10_a_a274 : std_logic;
SIGNAL count1_a11_a_a277 : std_logic;
SIGNAL count1_a11_a_a276 : std_logic;
SIGNAL count1_a12_a_a279 : std_logic;
SIGNAL count1_a12_a_a278 : std_logic;
SIGNAL count1_a13_a_a281 : std_logic;
SIGNAL count1_a13_a_a280 : std_logic;
SIGNAL count1_a14_a_a283 : std_logic;
SIGNAL count1_a14_a_a282 : std_logic;
SIGNAL count1_a15_a_a285 : std_logic;
SIGNAL count1_a15_a_a284 : std_logic;
SIGNAL count1_a16_a_a287 : std_logic;
SIGNAL count1_a16_a_a286 : std_logic;
SIGNAL count1_a17_a_a289 : std_logic;
SIGNAL count1_a17_a_a288 : std_logic;
SIGNAL count1_a18_a_a291 : std_logic;
SIGNAL count1_a18_a_a290 : std_logic;
SIGNAL count1_a19_a_a293 : std_logic;
SIGNAL count1_a19_a_a292 : std_logic;
SIGNAL count1_a20_a_a295 : std_logic;
SIGNAL count1_a20_a_a294 : std_logic;
SIGNAL count1_a21_a_a297 : std_logic;
SIGNAL count1_a21_a_a296 : std_logic;
SIGNAL count1_a22_a_a299 : std_logic;
SIGNAL count1_a22_a_a298 : std_logic;
SIGNAL count1_a23_a_a301 : std_logic;
SIGNAL count1_a23_a_a300 : std_logic;
SIGNAL count1_a24_a_a302 : std_logic;
SIGNAL add_a664 : std_logic;
SIGNAL qout_a3_a_a138 : std_logic;
SIGNAL clk_acombout : std_logic;
SIGNAL count1_a24_a_aclkctrl : std_logic;
SIGNAL clk_aclkctrl : std_logic;
SIGNAL reset_acombout : std_logic;
SIGNAL add_a660 : std_logic;
SIGNAL output_a4 : std_logic;
SIGNAL output_a4clkctrl : std_logic;
SIGNAL output_a1 : std_logic;
SIGNAL add_a661 : std_logic;
SIGNAL a_acounter2_aoutput_a2_a : std_logic;
SIGNAL mode_acombout : std_logic;
SIGNAL qout_a2_a_a136 : std_logic;
SIGNAL output_a5 : std_logic;
SIGNAL output_a5clkctrl : std_logic;
SIGNAL a_acounter2_aoutput_a0_a : std_logic;
SIGNAL qout_a0_a_a134 : std_logic;
SIGNAL output_a26 : std_logic;
SIGNAL output_a3 : std_logic;
SIGNAL add_a665 : std_logic;
SIGNAL output_a2 : std_logic;
SIGNAL qout_a1_a_a135 : std_logic;
SIGNAL add_a662 : std_logic;
SIGNAL output_a0 : std_logic;
SIGNAL add_a663 : std_logic;
SIGNAL a_acounter2_aoutput_a3_a : std_logic;
SIGNAL qout_a3_a_a137 : std_logic;
SIGNAL Mux_a165 : std_logic;
SIGNAL Mux_a166 : std_logic;
SIGNAL Mux_a167 : std_logic;
SIGNAL Mux_a168 : std_logic;
SIGNAL Mux_a169 : std_logic;
SIGNAL Mux_a170 : std_logic;
SIGNAL Mux_a171 : std_logic;
SIGNAL Mux_a172 : std_logic;
SIGNAL ALT_INV_Mux_a171 : std_logic;
SIGNAL ALT_INV_Mux_a172 : std_logic;

BEGIN

ww_mode <= mode;
ww_reset <= reset;
ww_clk <= clk;
hex0 <= ww_hex0;
hex1 <= ww_hex1;
modeout <= ww_modeout;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

output_a5clkctrl_I_INCLK_bus <= (gnd & gnd & gnd & output_a5);

output_a4clkctrl_I_INCLK_bus <= (gnd & gnd & gnd & output_a4);

count1_a24_a_aclkctrl_I_INCLK_bus <= (gnd & gnd & gnd & count1_a24_a);

clk_aclkctrl_I_INCLK_bus <= (gnd & gnd & gnd & clk_acombout);
ALT_INV_Mux_a171 <= NOT Mux_a171;
ALT_INV_Mux_a172 <= NOT Mux_a172;

a_acounter2_aoutput_a1_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => count1_a24_a_aclkctrl,
	datain => add_a665,
	aclr => output_a5clkctrl,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => a_acounter2_aoutput_a1_a);

count1_a24_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a24_a_a302,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a24_a);

clk_aI : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_clk,
	combout => clk_acombout);

count1_a23_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a23_a_a300,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a23_a);

count1_a22_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a22_a_a298,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a22_a);

count1_a21_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a21_a_a296,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a21_a);

count1_a20_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a20_a_a294,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a20_a);

count1_a19_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a19_a_a292,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a19_a);

count1_a18_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a18_a_a290,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a18_a);

count1_a17_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a17_a_a288,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a17_a);

count1_a16_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a16_a_a286,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a16_a);

count1_a15_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a15_a_a284,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a15_a);

count1_a14_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a14_a_a282,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a14_a);

count1_a13_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a13_a_a280,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a13_a);

count1_a12_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a12_a_a278,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a12_a);

count1_a11_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a11_a_a276,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a11_a);

count1_a10_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a10_a_a274,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a10_a);

count1_a9_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a9_a_a272,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a9_a);

count1_a8_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a8_a_a270,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a8_a);

count1_a7_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a7_a_a268,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a7_a);

count1_a6_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a6_a_a266,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a6_a);

count1_a5_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a5_a_a264,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a5_a);

count1_a4_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a4_a_a262,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a4_a);

count1_a3_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a3_a_a260,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a3_a);

count1_a2_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a2_a_a258,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a2_a);

count1_a1_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a1_a_a256,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a1_a);

count1_a0_a_aI : cycloneii_lcell_ff
PORT MAP (
	clk => clk_aclkctrl,
	datain => count1_a0_a_a254,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => count1_a0_a);

count1_a0_a_a254_I : cycloneii_lcell_comb
-- Equation(s):