seven_segment.vho

以QuatusⅡ为平台

-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "0000100110010000")
-- pragma translate_on
PORT MAP (
	pathsel => Mux_a165_I_pathsel,
	dataa => qout_a3_a_a137,
	datab => qout_a1_a_a135,
	datac => qout_a2_a_a136,
	datad => qout_a0_a_a134,
	cin => GND,
	modesel => Mux_a165_I_modesel,
	combout => Mux_a165);

Mux_a166_I : cycloneii_lcell_comb
-- Equation(s):
-- Mux_a166 = qout_a2_a_a136 & (qout_a3_a_a137 & qout_a1_a_a135 & qout_a0_a_a134 # !qout_a3_a_a137 & (qout_a1_a_a135 $ qout_a0_a_a134))

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "1001000001000000")
-- pragma translate_on
PORT MAP (
	pathsel => Mux_a166_I_pathsel,
	dataa => qout_a3_a_a137,
	datab => qout_a1_a_a135,
	datac => qout_a2_a_a136,
	datad => qout_a0_a_a134,
	cin => GND,
	modesel => Mux_a166_I_modesel,
	combout => Mux_a166);

Mux_a167_I : cycloneii_lcell_comb
-- Equation(s):
-- Mux_a167 = !qout_a0_a_a134 & (qout_a3_a_a137 & !qout_a1_a_a135 & qout_a2_a_a136 # !qout_a3_a_a137 & qout_a1_a_a135 & !qout_a2_a_a136)

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "0000000000100100")
-- pragma translate_on
PORT MAP (
	pathsel => Mux_a167_I_pathsel,
	dataa => qout_a3_a_a137,
	datab => qout_a1_a_a135,
	datac => qout_a2_a_a136,
	datad => qout_a0_a_a134,
	cin => GND,
	modesel => Mux_a167_I_modesel,
	combout => Mux_a167);

Mux_a168_I : cycloneii_lcell_comb
-- Equation(s):
-- Mux_a168 = qout_a0_a_a134 & (qout_a2_a_a136 $ (qout_a3_a_a137 # !qout_a1_a_a135)) # !qout_a0_a_a134 & qout_a2_a_a136 & (qout_a3_a_a137 $ !qout_a1_a_a135)

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "0100101110010000")
-- pragma translate_on
PORT MAP (
	pathsel => Mux_a168_I_pathsel,
	dataa => qout_a3_a_a137,
	datab => qout_a1_a_a135,
	datac => qout_a2_a_a136,
	datad => qout_a0_a_a134,
	cin => GND,
	modesel => Mux_a168_I_modesel,
	combout => Mux_a168);

Mux_a169_I : cycloneii_lcell_comb
-- Equation(s):
-- Mux_a169 = qout_a0_a_a134 # qout_a2_a_a136 & (qout_a1_a_a135 $ !qout_a3_a_a137)

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "1111111110000100")
-- pragma translate_on
PORT MAP (
	pathsel => Mux_a169_I_pathsel,
	dataa => qout_a1_a_a135,
	datab => qout_a2_a_a136,
	datac => qout_a3_a_a137,
	datad => qout_a0_a_a134,
	cin => GND,
	modesel => Mux_a169_I_modesel,
	combout => Mux_a169);

Mux_a170_I : cycloneii_lcell_comb
-- Equation(s):
-- Mux_a170 = qout_a1_a_a135 & (qout_a2_a_a136 & !qout_a3_a_a137 & qout_a0_a_a134 # !qout_a2_a_a136 & (qout_a0_a_a134 # !qout_a3_a_a137)) # !qout_a1_a_a135 & (qout_a2_a_a136 & qout_a3_a_a137 # !qout_a2_a_a136 & !qout_a3_a_a137 & qout_a0_a_a134)

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "0110101101000010")
-- pragma translate_on
PORT MAP (
	pathsel => Mux_a170_I_pathsel,
	dataa => qout_a1_a_a135,
	datab => qout_a2_a_a136,
	datac => qout_a3_a_a137,
	datad => qout_a0_a_a134,
	cin => GND,
	modesel => Mux_a170_I_modesel,
	combout => Mux_a170);

Mux_a171_I : cycloneii_lcell_comb
-- Equation(s):
-- Mux_a171 = qout_a2_a_a136 & (qout_a3_a_a137 # !qout_a0_a_a134 # !qout_a1_a_a135) # !qout_a2_a_a136 & (qout_a1_a_a135 $ qout_a3_a_a137)

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "1101011011011110")
-- pragma translate_on
PORT MAP (
	pathsel => Mux_a171_I_pathsel,
	dataa => qout_a1_a_a135,
	datab => qout_a2_a_a136,
	datac => qout_a3_a_a137,
	datad => qout_a0_a_a134,
	cin => GND,
	modesel => Mux_a171_I_modesel,
	combout => Mux_a171);

Mux_a172_I : cycloneii_lcell_comb
-- Equation(s):
-- Mux_a172 = !qout_a1_a_a135 & !qout_a2_a_a136 # !qout_a3_a_a137

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "0001111100011111")
-- pragma translate_on
PORT MAP (
	pathsel => Mux_a172_I_pathsel,
	dataa => qout_a1_a_a135,
	datab => qout_a2_a_a136,
	datac => qout_a3_a_a137,
	datad => VCC,
	cin => GND,
	modesel => Mux_a172_I_modesel,
	combout => Mux_a172);

hex0_a0_a_aI : cycloneii_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => Mux_a165,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	differentialin => GND,
	linkin => GND,
	modesel => hex0_a0_a_aI_modesel,
	padio => ww_hex0(0));

hex0_a1_a_aI : cycloneii_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => Mux_a166,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	differentialin => GND,
	linkin => GND,
	modesel => hex0_a1_a_aI_modesel,
	padio => ww_hex0(1));

hex0_a2_a_aI : cycloneii_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => Mux_a167,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	differentialin => GND,
	linkin => GND,
	modesel => hex0_a2_a_aI_modesel,
	padio => ww_hex0(2));

hex0_a3_a_aI : cycloneii_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => Mux_a168,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	differentialin => GND,
	linkin => GND,
	modesel => hex0_a3_a_aI_modesel,
	padio => ww_hex0(3));

hex0_a4_a_aI : cycloneii_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => Mux_a169,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	differentialin => GND,
	linkin => GND,
	modesel => hex0_a4_a_aI_modesel,
	padio => ww_hex0(4));

hex0_a5_a_aI : cycloneii_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => Mux_a170,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	differentialin => GND,
	linkin => GND,
	modesel => hex0_a5_a_aI_modesel,
	padio => ww_hex0(5));

hex0_a6_a_aI : cycloneii_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => ALT_INV_Mux_a171,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	differentialin => GND,
	linkin => GND,
	modesel => hex0_a6_a_aI_modesel,
	padio => ww_hex0(6));

hex1_a0_a_aI : cycloneii_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => ALT_INV_Mux_a172,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	differentialin => GND,
	linkin => GND,
	modesel => hex1_a0_a_aI_modesel,
	padio => ww_hex1(0));

hex1_a1_a_aI : cycloneii_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	differentialin => GND,
	linkin => GND,
	modesel => hex1_a1_a_aI_modesel,
	padio => ww_hex1(1));

hex1_a2_a_aI : cycloneii_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,