📄 seven_segment.vho
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Mux_a165_I_pathsel <= "00001111";
Mux_a166_I_modesel <= "1001";
Mux_a166_I_pathsel <= "00001111";
Mux_a167_I_modesel <= "1001";
Mux_a167_I_pathsel <= "00001111";
Mux_a168_I_modesel <= "1001";
Mux_a168_I_pathsel <= "00001111";
Mux_a169_I_modesel <= "1001";
Mux_a169_I_pathsel <= "00001111";
Mux_a170_I_modesel <= "1001";
Mux_a170_I_pathsel <= "00001111";
Mux_a171_I_modesel <= "1001";
Mux_a171_I_pathsel <= "00001111";
Mux_a172_I_modesel <= "1001";
Mux_a172_I_pathsel <= "00000111";
hex0_a0_a_aI_modesel <= "00000000000000000000000010";
hex0_a1_a_aI_modesel <= "00000000000000000000000010";
hex0_a2_a_aI_modesel <= "00000000000000000000000010";
hex0_a3_a_aI_modesel <= "00000000000000000000000010";
hex0_a4_a_aI_modesel <= "00000000000000000000000010";
hex0_a5_a_aI_modesel <= "00000000000000000000000010";
hex0_a6_a_aI_modesel <= "00000000000000000000000010";
hex1_a0_a_aI_modesel <= "00000000000000000000000010";
hex1_a1_a_aI_modesel <= "00000000000000000000000010";
hex1_a2_a_aI_modesel <= "00000000000000000000000010";
hex1_a3_a_aI_modesel <= "00000000000000000000000010";
hex1_a4_a_aI_modesel <= "00000000000000000000000010";
hex1_a5_a_aI_modesel <= "00000000000000000000000010";
hex1_a6_a_aI_modesel <= "00000000000000000000000010";
modeout_aI_modesel <= "00000000000000000000000010";
output_a5clkctrl_I_INCLK_bus <= (gnd & gnd & gnd & output_a5);
output_a4clkctrl_I_INCLK_bus <= (gnd & gnd & gnd & output_a4);
count1_a24_a_aclkctrl_I_INCLK_bus <= (gnd & gnd & gnd & count1_a24_a);
clk_aclkctrl_I_INCLK_bus <= (gnd & gnd & gnd & clk_acombout);
INV_INST_Mux_a171 : INV
PORT MAP (
IN1 => Mux_a171,
Y => ALT_INV_Mux_a171);
INV_INST_Mux_a172 : INV
PORT MAP (
IN1 => Mux_a172,
Y => ALT_INV_Mux_a172);
lcell_ff_enable_asynch_arcs : AND1
PORT MAP (
IN1 => GND,
Y => lcell_ff_enable_asynch_arcs_out);
a_acounter2_aoutput_a1_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => count1_a24_a_aclkctrl,
datain => add_a665,
sdata => GND,
aclr => output_a5clkctrl,
sclr => GND,
sload => GND,
ena => VCC,
regout => a_acounter2_aoutput_a1_a);
count1_a24_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a24_a_a302,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a24_a);
clk_aI : cycloneii_io
-- pragma translate_off
-- GENERIC MAP (
-- operation_mode => "input",
-- input_register_mode => "none",
-- output_register_mode => "none",
-- oe_register_mode => "none",
-- input_async_reset => "none",
-- output_async_reset => "none",
-- oe_async_reset => "none",
-- input_sync_reset => "none",
-- output_sync_reset => "none",
-- oe_sync_reset => "none",
-- input_power_up => "low",
-- output_power_up => "low",
-- oe_power_up => "low")
-- pragma translate_on
PORT MAP (
datain => GND,
oe => GND,
outclk => GND,
outclkena => VCC,
inclk => GND,
inclkena => VCC,
areset => GND,
sreset => GND,
differentialin => GND,
linkin => GND,
modesel => clk_aI_modesel,
combout => clk_acombout,
padio => ww_clk);
count1_a23_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a23_a_a300,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a23_a);
count1_a22_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a22_a_a298,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a22_a);
count1_a21_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a21_a_a296,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a21_a);
count1_a20_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a20_a_a294,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a20_a);
count1_a19_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a19_a_a292,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a19_a);
count1_a18_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a18_a_a290,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a18_a);
count1_a17_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a17_a_a288,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a17_a);
count1_a16_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a16_a_a286,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a16_a);
count1_a15_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a15_a_a284,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a15_a);
count1_a14_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a14_a_a282,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a14_a);
count1_a13_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a13_a_a280,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a13_a);
count1_a12_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a12_a_a278,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a12_a);
count1_a11_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a11_a_a276,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a11_a);
count1_a10_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a10_a_a274,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a10_a);
count1_a9_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a9_a_a272,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a9_a);
count1_a8_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a8_a_a270,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a8_a);
count1_a7_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a7_a_a268,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a7_a);
count1_a6_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a6_a_a266,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a6_a);
count1_a5_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a5_a_a264,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a5_a);
count1_a4_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a4_a_a262,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a4_a);
count1_a3_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a3_a_a260,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a3_a);
count1_a2_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a2_a_a258,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a2_a);
count1_a1_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a1_a_a256,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a1_a);
count1_a0_a_aI : cycloneii_lcell_ff
PORT MAP (
clk => clk_aclkctrl,
datain => count1_a0_a_a254,
sdata => GND,
aclr => GND,
sclr => GND,
sload => GND,
ena => VCC,
regout => count1_a0_a);
count1_a0_a_a254_I : cycloneii_lcell_comb
-- Equation(s):
-- count1_a0_a_a254 = count1_a0_a $ VCC
-- count1_a0_a_a255 = CARRY(count1_a0_a)
-- pragma translate_off
-- GENERIC MAP (
-- sum_lutc_input => "datac",
-- lut_mask => "0011001111001100")
-- pragma translate_on
PORT MAP (
pathsel => count1_a0_a_a254_I_pathsel,
dataa => VCC,
datab => count1_a0_a,
datac => VCC,
datad => VCC,
cin => GND,
modesel => count1_a0_a_a254_I_modesel,
combout => count1_a0_a_a254,
cout => count1_a0_a_a255);
count1_a1_a_a256_I : cycloneii_lcell_comb
-- Equation(s):
-- count1_a1_a_a256 = count1_a1_a & !count1_a0_a_a255 # !count1_a1_a & (count1_a0_a_a255 # GND)
-- count1_a1_a_a257 = CARRY(!count1_a0_a_a255 # !count1_a1_a)
-- pragma translate_off
-- GENERIC MAP (
-- sum_lutc_input => "cin",
-- lut_mask => "0101101001011111")
-- pragma translate_on
PORT MAP (
pathsel => count1_a1_a_a256_I_pathsel,
dataa => count1_a1_a,
datab => VCC,
datac => VCC,
datad => VCC,
cin => count1_a0_a_a255,
modesel => count1_a1_a_a256_I_modesel,
combout => count1_a1_a_a256,
cout => count1_a1_a_a257);
count1_a2_a_a258_I : cycloneii_lcell_comb
-- Equation(s):
-- count1_a2_a_a258 = count1_a2_a & (count1_a1_a_a257 $ GND) # !count1_a2_a & !count1_a1_a_a257 & VCC
-- count1_a2_a_a259 = CARRY(count1_a2_a & !count1_a1_a_a257)
-- pragma translate_off
-- GENERIC MAP (
-- sum_lutc_input => "cin",
-- lut_mask => "1010010100001010")
-- pragma translate_on
PORT MAP (
pathsel => count1_a2_a_a258_I_pathsel,
dataa => count1_a2_a,
datab => VCC,
datac => VCC,
datad => VCC,
cin => count1_a1_a_a257,
modesel => count1_a2_a_a258_I_modesel,
combout => count1_a2_a_a258,
cout => count1_a2_a_a259);
count1_a3_a_a260_I : cycloneii_lcell_comb
-- Equation(s):
-- count1_a3_a_a260 = count1_a3_a & !count1_a2_a_a259 # !count1_a3_a & (count1_a2_a_a259 # GND)
-- count1_a3_a_a261 = CARRY(!count1_a2_a_a259 # !count1_a3_a)
-- pragma translate_off
-- GENERIC MAP (
-- sum_lutc_input => "cin",
-- lut_mask => "0011110000111111")
-- pragma translate_on
PORT MAP (
pathsel => count1_a3_a_a260_I_pathsel,
dataa => VCC,
datab => count1_a3_a,
datac => VCC,
datad => VCC,
cin => count1_a2_a_a259,
modesel => count1_a3_a_a260_I_modesel,
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