seven_segment.vho

以QuatusⅡ为平台

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.0 Build 148 04/26/2005 SJ Web Edition"

-- DATE "11/28/2007 15:34:31"

-- 
-- Device: Altera EP2C35F672C6 Package FBGA672
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	seven_segment IS
    PORT (
	mode : IN std_logic;
	reset : IN std_logic;
	clk : IN std_logic;
	hex0 : OUT std_logic_vector(6 DOWNTO 0);
	hex1 : OUT std_logic_vector(6 DOWNTO 0);
	modeout : OUT std_logic
	);
END seven_segment;

ARCHITECTURE structure OF seven_segment IS
SIGNAL GNDs : std_logic_vector(255 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(255 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_mode : std_logic;
SIGNAL ww_reset : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_hex0 : std_logic_vector(6 DOWNTO 0);
SIGNAL ww_hex1 : std_logic_vector(6 DOWNTO 0);
SIGNAL ww_modeout : std_logic;
SIGNAL output_a5clkctrl_I_INCLK_bus : std_logic_vector(3 DOWNTO 0);
SIGNAL output_a4clkctrl_I_INCLK_bus : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a24_a_aclkctrl_I_INCLK_bus : std_logic_vector(3 DOWNTO 0);
SIGNAL clk_aclkctrl_I_INCLK_bus : std_logic_vector(3 DOWNTO 0);
SIGNAL clk_aI_modesel : std_logic_vector(25 DOWNTO 0);
SIGNAL count1_a0_a_a254_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a0_a_a254_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a1_a_a256_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a1_a_a256_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a2_a_a258_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a2_a_a258_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a3_a_a260_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a3_a_a260_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a4_a_a262_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a4_a_a262_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a5_a_a264_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a5_a_a264_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a6_a_a266_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a6_a_a266_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a7_a_a268_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a7_a_a268_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a8_a_a270_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a8_a_a270_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a9_a_a272_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a9_a_a272_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a10_a_a274_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a10_a_a274_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a11_a_a276_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a11_a_a276_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a12_a_a278_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a12_a_a278_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a13_a_a280_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a13_a_a280_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a14_a_a282_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a14_a_a282_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a15_a_a284_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a15_a_a284_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a16_a_a286_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a16_a_a286_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a17_a_a288_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a17_a_a288_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a18_a_a290_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a18_a_a290_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a19_a_a292_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a19_a_a292_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a20_a_a294_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a20_a_a294_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a21_a_a296_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a21_a_a296_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a22_a_a298_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a22_a_a298_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a23_a_a300_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a23_a_a300_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a24_a_a302_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL count1_a24_a_a302_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL add_a664_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL add_a664_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL qout_a3_a_a138_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL qout_a3_a_a138_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL count1_a24_a_aclkctrl_I_modesel : std_logic;
SIGNAL clk_aclkctrl_I_modesel : std_logic;
SIGNAL reset_aI_modesel : std_logic_vector(25 DOWNTO 0);
SIGNAL add_a660_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL add_a660_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL output_a4_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL output_a4_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL output_a4clkctrl_I_modesel : std_logic;
SIGNAL add_a661_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL add_a661_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL mode_aI_modesel : std_logic_vector(25 DOWNTO 0);
SIGNAL qout_a2_a_a136_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL qout_a2_a_a136_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL output_a5_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL output_a5_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL output_a5clkctrl_I_modesel : std_logic;
SIGNAL qout_a0_a_a134_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL qout_a0_a_a134_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL output_a26_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL output_a26_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL add_a665_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL add_a665_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL qout_a1_a_a135_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL qout_a1_a_a135_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL add_a662_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL add_a662_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL add_a663_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL add_a663_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL qout_a3_a_a137_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL qout_a3_a_a137_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL Mux_a165_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL Mux_a165_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL Mux_a166_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL Mux_a166_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL Mux_a167_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL Mux_a167_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL Mux_a168_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL Mux_a168_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL Mux_a169_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL Mux_a169_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL Mux_a170_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL Mux_a170_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL Mux_a171_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL Mux_a171_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL Mux_a172_I_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL Mux_a172_I_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL hex0_a0_a_aI_modesel : std_logic_vector(25 DOWNTO 0);
SIGNAL hex0_a1_a_aI_modesel : std_logic_vector(25 DOWNTO 0);
SIGNAL hex0_a2_a_aI_modesel : std_logic_vector(25 DOWNTO 0);
SIGNAL hex0_a3_a_aI_modesel : std_logic_vector(25 DOWNTO 0);
SIGNAL hex0_a4_a_aI_modesel : std_logic_vector(25 DOWNTO 0);
SIGNAL hex0_a5_a_aI_modesel : std_logic_vector(25 DOWNTO 0);
SIGNAL hex0_a6_a_aI_modesel : std_logic_vector(25 DOWNTO 0);
SIGNAL hex1_a0_a_aI_modesel : std_logic_vector(25 DOWNTO 0);
SIGNAL hex1_a1_a_aI_modesel : std_logic_vector(25 DOWNTO 0);
SIGNAL hex1_a2_a_aI_modesel : std_logic_vector(25 DOWNTO 0);
SIGNAL hex1_a3_a_aI_modesel : std_logic_vector(25 DOWNTO 0);
SIGNAL hex1_a4_a_aI_modesel : std_logic_vector(25 DOWNTO 0);
SIGNAL hex1_a5_a_aI_modesel : std_logic_vector(25 DOWNTO 0);
SIGNAL hex1_a6_a_aI_modesel : std_logic_vector(25 DOWNTO 0);
SIGNAL modeout_aI_modesel : std_logic_vector(25 DOWNTO 0);
SIGNAL a_acounter2_aoutput_a1_a : std_logic;
SIGNAL count1_a24_a : std_logic;
SIGNAL count1_a23_a : std_logic;
SIGNAL count1_a22_a : std_logic;
SIGNAL count1_a21_a : std_logic;
SIGNAL count1_a20_a : std_logic;
SIGNAL count1_a19_a : std_logic;
SIGNAL count1_a18_a : std_logic;
SIGNAL count1_a17_a : std_logic;
SIGNAL count1_a16_a : std_logic;
SIGNAL count1_a15_a : std_logic;
SIGNAL count1_a14_a : std_logic;
SIGNAL count1_a13_a : std_logic;
SIGNAL count1_a12_a : std_logic;
SIGNAL count1_a11_a : std_logic;
SIGNAL count1_a10_a : std_logic;
SIGNAL count1_a9_a : std_logic;
SIGNAL count1_a8_a : std_logic;
SIGNAL count1_a7_a : std_logic;
SIGNAL count1_a6_a : std_logic;
SIGNAL count1_a5_a : std_logic;
SIGNAL count1_a4_a : std_logic;
SIGNAL count1_a3_a : std_logic;
SIGNAL count1_a2_a : std_logic;
SIGNAL count1_a1_a : std_logic;
SIGNAL count1_a0_a : std_logic;
SIGNAL count1_a0_a_a255 : std_logic;
SIGNAL count1_a0_a_a254 : std_logic;
SIGNAL count1_a1_a_a257 : std_logic;
SIGNAL count1_a1_a_a256 : std_logic;
SIGNAL count1_a2_a_a259 : std_logic;
SIGNAL count1_a2_a_a258 : std_logic;
SIGNAL count1_a3_a_a261 : std_logic;
SIGNAL count1_a3_a_a260 : std_logic;
SIGNAL count1_a4_a_a263 : std_logic;
SIGNAL count1_a4_a_a262 : std_logic;
SIGNAL count1_a5_a_a265 : std_logic;
SIGNAL count1_a5_a_a264 : std_logic;
SIGNAL count1_a6_a_a267 : std_logic;
SIGNAL count1_a6_a_a266 : std_logic;
SIGNAL count1_a7_a_a269 : std_logic;
SIGNAL count1_a7_a_a268 : std_logic;
SIGNAL count1_a8_a_a271 : std_logic;
SIGNAL count1_a8_a_a270 : std_logic;
SIGNAL count1_a9_a_a273 : std_logic;
SIGNAL count1_a9_a_a272 : std_logic;
SIGNAL count1_a10_a_a275 : std_logic;
SIGNAL count1_a10_a_a274 : std_logic;
SIGNAL count1_a11_a_a277 : std_logic;
SIGNAL count1_a11_a_a276 : std_logic;
SIGNAL count1_a12_a_a279 : std_logic;
SIGNAL count1_a12_a_a278 : std_logic;
SIGNAL count1_a13_a_a281 : std_logic;
SIGNAL count1_a13_a_a280 : std_logic;
SIGNAL count1_a14_a_a283 : std_logic;
SIGNAL count1_a14_a_a282 : std_logic;
SIGNAL count1_a15_a_a285 : std_logic;
SIGNAL count1_a15_a_a284 : std_logic;
SIGNAL count1_a16_a_a287 : std_logic;
SIGNAL count1_a16_a_a286 : std_logic;
SIGNAL count1_a17_a_a289 : std_logic;
SIGNAL count1_a17_a_a288 : std_logic;
SIGNAL count1_a18_a_a291 : std_logic;
SIGNAL count1_a18_a_a290 : std_logic;
SIGNAL count1_a19_a_a293 : std_logic;
SIGNAL count1_a19_a_a292 : std_logic;
SIGNAL count1_a20_a_a295 : std_logic;
SIGNAL count1_a20_a_a294 : std_logic;
SIGNAL count1_a21_a_a297 : std_logic;
SIGNAL count1_a21_a_a296 : std_logic;
SIGNAL count1_a22_a_a299 : std_logic;
SIGNAL count1_a22_a_a298 : std_logic;
SIGNAL count1_a23_a_a301 : std_logic;
SIGNAL count1_a23_a_a300 : std_logic;
SIGNAL count1_a24_a_a302 : std_logic;
SIGNAL add_a664 : std_logic;
SIGNAL qout_a3_a_a138 : std_logic;
SIGNAL clk_acombout : std_logic;
SIGNAL count1_a24_a_aclkctrl : std_logic;
SIGNAL clk_aclkctrl : std_logic;
SIGNAL reset_acombout : std_logic;
SIGNAL add_a660 : std_logic;
SIGNAL output_a4 : std_logic;
SIGNAL output_a4clkctrl : std_logic;
SIGNAL output_a1 : std_logic;
SIGNAL add_a661 : std_logic;
SIGNAL a_acounter2_aoutput_a2_a : std_logic;
SIGNAL mode_acombout : std_logic;
SIGNAL qout_a2_a_a136 : std_logic;
SIGNAL output_a5 : std_logic;
SIGNAL output_a5clkctrl : std_logic;
SIGNAL a_acounter2_aoutput_a0_a : std_logic;
SIGNAL qout_a0_a_a134 : std_logic;
SIGNAL output_a26 : std_logic;
SIGNAL output_a3 : std_logic;
SIGNAL add_a665 : std_logic;
SIGNAL output_a2 : std_logic;
SIGNAL qout_a1_a_a135 : std_logic;
SIGNAL add_a662 : std_logic;
SIGNAL output_a0 : std_logic;
SIGNAL add_a663 : std_logic;
SIGNAL a_acounter2_aoutput_a3_a : std_logic;
SIGNAL qout_a3_a_a137 : std_logic;
SIGNAL Mux_a165 : std_logic;
SIGNAL Mux_a166 : std_logic;
SIGNAL Mux_a167 : std_logic;
SIGNAL Mux_a168 : std_logic;
SIGNAL Mux_a169 : std_logic;
SIGNAL Mux_a170 : std_logic;
SIGNAL Mux_a171 : std_logic;
SIGNAL Mux_a172 : std_logic;
SIGNAL ALT_INV_Mux_a171 : std_logic;
SIGNAL ALT_INV_Mux_a172 : std_logic;
COMPONENT cycloneii_lcell_comb
PORT (
	dataa : IN STD_LOGIC;
	datab : IN STD_LOGIC;
	datac : IN STD_LOGIC;
	datad : IN STD_LOGIC;
	cin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	cout : OUT STD_LOGIC;
	MODESEL : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	PATHSEL : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;

COMPONENT cycloneii_lcell_ff
PORT (
	clk : IN STD_LOGIC;
	datain : IN STD_LOGIC;
	sdata : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	sclr : IN STD_LOGIC;
	sload : IN STD_LOGIC;
	ena : IN STD_LOGIC;
	regout : OUT STD_LOGIC);
END COMPONENT;

COMPONENT cycloneii_io
PORT (
	datain : IN STD_LOGIC;
	oe : IN STD_LOGIC;
	outclk : IN STD_LOGIC;
	outclkena : IN STD_LOGIC;
	inclk : IN STD_LOGIC;
	inclkena : IN STD_LOGIC;
	areset : IN STD_LOGIC;
	sreset : IN STD_LOGIC;
	differentialin : IN STD_LOGIC;
	linkin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	differentialout : OUT STD_LOGIC;
	linkout : OUT STD_LOGIC;
	padio : INOUT STD_LOGIC;
	MODESEL : IN STD_LOGIC_VECTOR(25 DOWNTO 0));
END COMPONENT;

COMPONENT cycloneii_clkctrl
PORT (
	ena : IN STD_LOGIC;
	inclk : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	clkselect : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	outclk : OUT STD_LOGIC;
	MODESEL : IN STD_LOGIC);
END COMPONENT;


COMPONENT INV
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;
BEGIN

ww_mode <= mode;
ww_reset <= reset;
ww_clk <= clk;
hex0 <= ww_hex0;
hex1 <= ww_hex1;
modeout <= ww_modeout;

gnd <= '0';
vcc <= '1';
GNDs <= (OTHERS => '0');
VCCs <= (OTHERS => '1');

clk_aI_modesel <= "00000000000000000000000001";
count1_a0_a_a254_I_modesel <= "1011";
count1_a0_a_a254_I_pathsel <= "01001010";
count1_a1_a_a256_I_modesel <= "0111";
count1_a1_a_a256_I_pathsel <= "10111001";
count1_a2_a_a258_I_modesel <= "0111";
count1_a2_a_a258_I_pathsel <= "10111001";
count1_a3_a_a260_I_modesel <= "0111";
count1_a3_a_a260_I_pathsel <= "11011010";
count1_a4_a_a262_I_modesel <= "0111";
count1_a4_a_a262_I_pathsel <= "10111001";
count1_a5_a_a264_I_modesel <= "0111";
count1_a5_a_a264_I_pathsel <= "11011010";
count1_a6_a_a266_I_modesel <= "0111";
count1_a6_a_a266_I_pathsel <= "10111001";
count1_a7_a_a268_I_modesel <= "0111";
count1_a7_a_a268_I_pathsel <= "11011010";
count1_a8_a_a270_I_modesel <= "0111";
count1_a8_a_a270_I_pathsel <= "10111001";
count1_a9_a_a272_I_modesel <= "0111";
count1_a9_a_a272_I_pathsel <= "11011010";
count1_a10_a_a274_I_modesel <= "0111";
count1_a10_a_a274_I_pathsel <= "11011010";
count1_a11_a_a276_I_modesel <= "0111";
count1_a11_a_a276_I_pathsel <= "11011010";
count1_a12_a_a278_I_modesel <= "0111";
count1_a12_a_a278_I_pathsel <= "11011010";
count1_a13_a_a280_I_modesel <= "0111";
count1_a13_a_a280_I_pathsel <= "11011010";
count1_a14_a_a282_I_modesel <= "0111";
count1_a14_a_a282_I_pathsel <= "11011010";
count1_a15_a_a284_I_modesel <= "0111";
count1_a15_a_a284_I_pathsel <= "10111001";
count1_a16_a_a286_I_modesel <= "0111";
count1_a16_a_a286_I_pathsel <= "11011010";
count1_a17_a_a288_I_modesel <= "0111";
count1_a17_a_a288_I_pathsel <= "10111001";
count1_a18_a_a290_I_modesel <= "0111";
count1_a18_a_a290_I_pathsel <= "10111001";
count1_a19_a_a292_I_modesel <= "0111";
count1_a19_a_a292_I_pathsel <= "11011010";
count1_a20_a_a294_I_modesel <= "0111";
count1_a20_a_a294_I_pathsel <= "10111001";
count1_a21_a_a296_I_modesel <= "0111";
count1_a21_a_a296_I_pathsel <= "11011010";
count1_a22_a_a298_I_modesel <= "0111";
count1_a22_a_a298_I_pathsel <= "10111001";
count1_a23_a_a300_I_modesel <= "0111";
count1_a23_a_a300_I_pathsel <= "11011010";
count1_a24_a_a302_I_modesel <= "0101";
count1_a24_a_a302_I_pathsel <= "00010001";
add_a664_I_modesel <= "1001";
add_a664_I_pathsel <= "00001111";
qout_a3_a_a138_I_modesel <= "1001";
qout_a3_a_a138_I_pathsel <= "00001111";
count1_a24_a_aclkctrl_I_modesel <= '0';
clk_aclkctrl_I_modesel <= '0';
reset_aI_modesel <= "00000000000000000000000001";
add_a660_I_modesel <= "1001";
add_a660_I_pathsel <= "00001110";
output_a4_I_modesel <= "1001";
output_a4_I_pathsel <= "00001111";
output_a4clkctrl_I_modesel <= '0';
add_a661_I_modesel <= "1001";
add_a661_I_pathsel <= "00001110";
mode_aI_modesel <= "00000000000000000000000001";
qout_a2_a_a136_I_modesel <= "1001";
qout_a2_a_a136_I_pathsel <= "00001110";
output_a5_I_modesel <= "1001";
output_a5_I_pathsel <= "00001111";
output_a5clkctrl_I_modesel <= '0';
qout_a0_a_a134_I_modesel <= "1001";
qout_a0_a_a134_I_pathsel <= "00001110";
output_a26_I_modesel <= "1001";
output_a26_I_pathsel <= "00001000";
add_a665_I_modesel <= "1001";
add_a665_I_pathsel <= "00001111";
qout_a1_a_a135_I_modesel <= "1001";
qout_a1_a_a135_I_pathsel <= "00001101";
add_a662_I_modesel <= "1001";
add_a662_I_pathsel <= "00001111";
add_a663_I_modesel <= "1001";
add_a663_I_pathsel <= "00001111";
qout_a3_a_a137_I_modesel <= "1001";
qout_a3_a_a137_I_pathsel <= "00001110";
Mux_a165_I_modesel <= "1001";