sysmotfcc2end.c

该源码为mpc8248处理器的BSP

    MII_READ(pPhyInfo->phyAddr,21,&miiIntStatusReg,tmp);
    ++miiNumLinkChgInts;
    
    fccFuncs.miiPhyInt(pPhyInfo->pDrvCtrl);
    
    }

/***********************************************************************
*
* sysMiiPhyInit - initialize and configure the PHY devices
*
* This routine scans, initializes and configures the PHY device.
*
* RETURNS: OK, or ERROR.
*/


LOCAL STATUS sysMiiPhyInit
    (
    PHY_INFO * pPhyInfo
    )
    {
    int    retVal,tmp;
    VUINT16 miiSpecial,miiIntEnableReg;
#ifdef CTDB_MPC8280
    return 0;
#endif

    retVal = miiPhyInit (pPhyInfo);

    if (retVal == OK)
        {
        MII_READ(pPhyInfo->phyAddr,18,&miiIntEnableReg,tmp);

        if (tmp == OK)
            {
            intConnect (INUM_TO_IVEC(INUM_IRQ5),sysMiiInt,(int)pPhyInfo);
            miiIntEnableReg = 0x0800; /* Full Duplex interrupt */
            MII_WRITE(pPhyInfo->phyAddr, 21, miiIntEnableReg, tmp);
            if (tmp == OK)
                {
                intEnable (INUM_IRQ5);
                }
            }
        }

    miiSpecial = 0x0400;
    MII_WRITE(pPhyInfo->phyAddr,16,miiSpecial,retVal);

    return retVal;
    }

/***********************************************************************
*
* sysFccEnetEnable - enable the MII interface to the FCC controller
*
* This routine is expected to perform any target specific functions required
* to enable the Ethernet device and to connect the MII interface to the FCC.
*
* RETURNS: OK, or ERROR if the FCC controller cannot be enabled.
*/

STATUS sysFccEnetEnable
    (
    UINT32  immrVal,    /* base address of the on-chip RAM */
    UINT8   fccNum  /* FCC being used */
    )
    {
    int             intLevel;

    intLevel = intLock ();


    /* assert the enable signal */

    if (fccNum==2)
      {

	*M8260_IOP_PCPAR(immrVal) |=  (PC17 | PC16);
	*M8260_IOP_PCSO(immrVal)  &= ~(PC17 | PC16);
	*M8260_IOP_PCDIR(immrVal) &= ~(PC17 | PC16);

	*M8260_IOP_PBPAR(immrVal) |=  (PB31 | PB30 | PB29 | PB28 | PB27 | 
				       PB26 | PB25 | PB24 | PB23 | PB22 | 
				       PB21 | PB20 | PB19 | PB18);
	*M8260_IOP_PBDIR(immrVal) |=  (PB31 | PB29 | PB25 | PB24 | PB23 | 
				       PB22);
	*M8260_IOP_PBDIR(immrVal) &= ~(PB30 | PB28 | PB27 | PB26 | PB21 | 
				       PB20 | PB19 | PB18);
	*M8260_IOP_PBSO(immrVal)  &= ~(PB31 | PB30 | PB28 | PB27 | PB26 | 
				       PB25 | PB24 | PB23 | PB22 | PB21 | 
				       PB20 | PB19 | PB18);
	*M8260_IOP_PBSO(immrVal)  |=  (PB29);

	/* connect FCC2 clocks */

	*M8260_CMXFCR (immrVal)  &= ~0xff0000;
	*M8260_CMXFCR (immrVal)  |= (M8260_CMXFCR_R2CS_CLK15 | 
				     M8260_CMXFCR_T2CS_CLK16);
	*M8260_CMXFCR (immrVal)  &= ~(M8260_CMXFCR_FC2_MUX);
    }
#ifdef CTDB_MPC8280
    if (fccNum==1)
      {
	*M8260_IOP_PCPAR(immrVal) |=  (PC20 | PC21);
	*M8260_IOP_PCSO(immrVal)  &= ~(PC20 | PC21);
	*M8260_IOP_PCDIR(immrVal) &= ~(PC20 | PC21);


       *M8260_IOP_PAPAR(immrVal)  &= ~ 0x3fc3f;
       *M8260_IOP_PAPAR(immrVal)  |=  0x3fc1f;
       *M8260_IOP_PASO(immrVal) &=~0x3fc3f;
       *M8260_IOP_PASO(immrVal) |=0x3f;
       *M8260_IOP_PADIR(immrVal) &=~0x3fc3f;
       *M8260_IOP_PADIR(immrVal) |=  0x00003c0c;


	/* connect FCC1 clocks */

	*M8260_CMXFCR (immrVal)  &= ~0xff000000;
	*M8260_CMXFCR (immrVal)  |= (M8260_CMXFCR_R1CS_CLK11 | 
				     M8260_CMXFCR_T1CS_CLK12);

	*M8260_CMXFCR (immrVal)  &= ~(M8260_CMXFCR_FC1_MUX);

    }
#else

    if (fccNum==1)
      {

	*M8260_IOP_PCPAR(immrVal) |=  (PC21 | PC22);
	*M8260_IOP_PCSO(immrVal)  &= ~(PC21 | PC22);
	*M8260_IOP_PCDIR(immrVal) &= ~(PC21 | PC22);

	*M8260_IOP_PASO(immrVal) |= (PD29 | PA28 | PA27 | PA26);	
	*M8260_IOP_PADIR(immrVal) |= (PB29 | PB28 | PB21 | PB20 | PB19 | PB18);
	*M8260_IOP_PCSO(immrVal) |= (PC15 | PC14 | PC13 | PC12 | PC7 | PC6);
	*M8260_IOP_PCDIR(immrVal) |= (PC15 | PC14 | PC13 | PC12 | PC7 | PC6); 
	*M8260_IOP_PDSO(immrVal) |= (PD29 | PD7);	
	*M8260_IOP_PDDIR(immrVal) |= (PD29 | PD19 | PD18 | PD7);	
	*M8260_IOP_PAPAR(immrVal) = (PA29 | PA28 | PA27 | PA26 | PA21 | PA20 |PA19 | PA18 | PA17 | PA16 | PA15 | PA14);	
	*M8260_IOP_PCPAR(immrVal) |= (PC15 | PC14 | PC13 | PC12 | PC7 | PC6);	
	*M8260_IOP_PDPAR(immrVal) |= (PD29 | PD19 | PD18);	
    
	/* connect FCC1 clocks */

	*M8260_CMXFCR (immrVal)  &= ~0xff000000;
	*M8260_CMXFCR (immrVal)  |= (M8260_CMXFCR_R1CS_CLK11 | 
				 M8260_CMXFCR_T1CS_CLK10);

	/* NMSI mode */

	*M8260_CMXFCR (immrVal)  &= ~(M8260_CMXFCR_FC1_MUX);         
      }
#endif

    intUnlock (intLevel);

    taskDelay (sysClkRateGet() >> 2);


    return(OK);
    }

/***********************************************************************
*
* sysFccEnetDisable - disable MII interface to the FCC controller
*
* This routine is expected to perform any target specific functions required
* to disable the Ethernet device and the MII interface to the FCC
* controller.  This involves restoring the default values for all the Port
* B and C signals.
*
* RETURNS: OK, always.
*/

STATUS sysFccEnetDisable
    (
    UINT32  immrVal,    /* base address of the on-chip RAM */
    UINT8   fccNum  /* FCC being used */
    )
    {
    volatile UINT32 tmp;
    int             intLevel;

    intLevel = intLock ();

    /*
     * configure all Port B and C pins previously used as general
     * purpose input pins
     */

    *M8260_IOP_PBPAR(immrVal) &= ~(PB15 | PB14);    /* clear PAR bits for xcvr RST and PWRDWN pins */
    *M8260_IOP_PBDIR(immrVal) |=  (PB15 | PB14);    /* make them outputs */

    tmp = *M8260_IOP_PBDAT(immrVal);        /* get current port B data */
    tmp |=  (PB14);         /* drive the active high PWRWN pin high */
    tmp &= ~(PB15);         /* drive the active low RST low too */
    *M8260_IOP_PBDAT(immrVal) = tmp;



    if (fccNum==2)
        {
	*M8260_IOP_PCPAR(immrVal) &= ~(PC17 | PC16);

	*M8260_IOP_PCDIR(immrVal) &= ~(PC10);

	*M8260_IOP_PBPAR(immrVal) &= ~(PB31 | PB30 | PB29 | PB28 | PB27 | 
				       PB26 | PB25 | PB24 | PB23 | PB22 | 
				       PB21 | PB20 | PB19 | PB18);
	*M8260_IOP_PBDIR(immrVal) &= ~(PB31 | PB29 | PB25 | PB24 | PB23 | 
				       PB22);
        /* Disable the interrupt */
	intDisable (INUM_FCC2);
	}
#ifdef CTDB_MPC8280

    if (fccNum==1)
      {

	*M8260_IOP_PCPAR(immrVal) &= ~ (PC20 | PC21);

       *M8260_IOP_PAPAR(immrVal)  &= ~ 0x3fc3f;

	 /* Disable the interrupt */
	intDisable (INUM_FCC1);
    }
#else
    if (fccNum==1)
        {
	*M8260_IOP_PCPAR(immrVal) &=  ~(PC21 | PC22);

	*M8260_IOP_PASO(immrVal) &= ~(PD29 | PA28 | PA27 | PA26);	
	*M8260_IOP_PADIR(immrVal) &= ~(PB29 | PB28 | PB21 | PB20 | PB19 | PB18);
	*M8260_IOP_PCSO(immrVal) &= ~(PC15 | PC14 | PC13 | PC12 | PC7 | PC6);
	*M8260_IOP_PCDIR(immrVal) &= ~(PC15 | PC14 | PC13 | PC12 | PC7 | PC6); 
	*M8260_IOP_PDSO(immrVal) &= ~(PD29 | PD7);	
	*M8260_IOP_PDDIR(immrVal) &= ~(PD29 | PD19 | PD18 | PD7);	
	*M8260_IOP_PAPAR(immrVal) &= ~(PA29 | PA28 | PA27 | PA26 | PA21 | PA20 |PA19 | PA18 | PA17 | PA16 | PA15 | PA14);	
	*M8260_IOP_PCPAR(immrVal) &= ~(PC15 | PC14 | PC13 | PC12 | PC7 | PC6);	
	*M8260_IOP_PDPAR(immrVal) &= ~(PD29 | PD19 | PD18);
	 /* Disable the interrupt */
	intDisable (INUM_FCC1);
	}
#endif
    intUnlock (intLevel);

    return(OK);
    }


/***********************************************************************
*
* sysFccEnetCommand - issue a command to the Ethernet interface controller
*
* RETURNS: OK, or ERROR if the Ethernet controller could not be restarted.
*/

STATUS sysFccEnetCommand
    (
    UINT32      immrVal,        /* base address of the on-chip RAM */
    UINT8   fccNum,     /* FCC being used */
    UINT16  command
    )
    {
    return (OK);
    }

#ifndef NSDELAY
#define MOTOROLA_FCC_LOOP_NS 2

#define NSDELAY(nsec)                                                   \
    {                                                                   \
    volatile int nx = 0;                                                \
    volatile int loop = (int)(nsec*MOTOROLA_FCC_LOOP_NS);               \
                                                                        \
    for (nx = 0; nx < loop; nx++);                                      \
    }
#endif /* NSDELAY */

/***********************************************************************
*
* sysFccMiiBitWr - write one bit to the MII interface
*
* This routine writes the value in <bitVal> to the MDIO line of a MII
* interface. The MDC line is asserted for a while, and then negated.
* If <bitVal> is NONE, then the MDIO pin should be left in high-impedance
* state.
*
* SEE ALSO: sysFccMiiBitRd()
*
* RETURNS: OK, or ERROR.
*/
STATUS sysFccMiiBitWr
    (
    UINT32      immrVal,        /* base address of the on-chip RAM */
    UINT8   fccNum,     /* FCC being used */
    INT32        bitVal          /* the bit being written */
    )
    {
    miiBitWrCount++;
    /*
     * we create the timing reference for transfer of info on the MDIO line
     * MDIO is mapped on PC18, MDC on PC19. We need to keep the same data
     * on MDIO for at least 400 nsec.
     */

    *M8260_IOP_PCPAR(immrVal) &= ~(PC19 | PC18);
    *M8260_IOP_PCDIR(immrVal) |= (PC19 | PC18);
    *M8260_IOP_PCDAT(immrVal) |= (PC19);

    switch (bitVal)
    {
    case 0:
        *M8260_IOP_PCDAT(immrVal) &= ~(PC18);
        break;
    case 1:
        *M8260_IOP_PCDAT(immrVal) |= (PC18);
        break;
    case ((INT32) NONE):
        /* put it in high-impedance state */
        *M8260_IOP_PCDIR(immrVal) &= ~(PC18);
        break;
    default:
        return (ERROR);
    }

    /* delay about 200 nsec. */

    NSDELAY (200);

    /* now we toggle the clock and delay again */

    *M8260_IOP_PCDAT(immrVal) &= ~(PC19);

    NSDELAY (200);

    return (OK);
    }

/***********************************************************************
*
* sysFccMiiBitRd - read one bit from the MII interface
*
* This routine reads one bit from the MDIO line of a MII
* interface. The MDC line is asserted for a while, and then negated.
*
* SEE ALSO: sysFccMiiBitWr()
*
* RETURNS: OK, or ERROR.
*/

STATUS sysFccMiiBitRd
    (
    UINT32      immrVal,        /* base address of the on-chip RAM */
    UINT8   fccNum,     /* FCC being used */
    INT8 *      bitVal          /* the bit being read */
    )
    {
    miiBitRdCount++;
    /*
     * we create the timing reference for transfer of info on the MDIO line
     * MDIO is mapped on PC18, MDC on PC19. We can read data on MDIO after
     * at least 400 nsec.
     */

    *M8260_IOP_PCPAR(immrVal) &= ~(PC19 | PC18);
    *M8260_IOP_PCDIR(immrVal) &= ~(PC18);

    *M8260_IOP_PCDIR(immrVal) |= (PC19);
    *M8260_IOP_PCDAT(immrVal) |= (PC19);

    /* delay about 200 nsec. */

    NSDELAY (200);

    /* now we toggle the clock and delay again */

    *M8260_IOP_PCDAT(immrVal) &= ~(PC19);

    NSDELAY (200);

    /* we can now read the MDIO data on PC18 */

    *bitVal = (*M8260_IOP_PCDAT(immrVal) & (PC18)) >> 13;

    return (OK);
    }
#ifdef CTDB_MPC8280
#include "i2c.c"
#endif
#endif /* INCLUDE_MOTFCCEND */