ads827x.h.bak

该源码为mpc8248处理器的BSP

/* ads827x.h - Motorola MPC827x ADS board header */

/* Copyright 1984-2003 Wind River Systems, Inc. */

/*
modification history
--------------------
01c,28jan04,dtr  Adding defines for DPRAM.
01b,08jan04,dtr  Adding in SEC registers.
01a,18dec03,dtr  adapted from ads826x.h
*/

/*
This file contains I/O addresses and related constants for the
Motorola MPC8272 ADS board.
*/

#ifndef	INCads827xh
#define	INCads827xh

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

#include "drv/intrCtl/m8260IntrCtl.h"

#define EIEIO_SYNC WRS_ASM (" eieio; sync")

#define M82XX_STANDARD_DPRAM_START 0x100
#define M82XX_STANDARD_DPRAM_LIMIT 0x1000
#define M82XX_FCC_DPRAM_START 0x1000
#define M82XX_FCC_DPRAM_LIMIT 0x2000

#define SPD_DATA_SIZE         128
#undef  BOOT_LINE_SIZE
#define BOOT_LINE_SIZE        256
#undef  NV_RAM_SIZE
#define NV_RAM_SIZE           256  
#define NV_RAM_SIZE_WRITEABLE NV_RAM_SIZE  /* force VTS to only use 128 bytes */
#define NV_RAM_READ(x)        sysNvRead (x)
#define NV_RAM_WRITE(x,y)     sysNvWrite (x,y)

/* add PCI access macros */
#define PCI_MEMIO2LOCAL(x) \
    (uint32_t)(((VUINT32)(x)  - PCI_MEMIO_ADRS) + CPU_PCI_MEMIO_ADRS)


/* PCI IO memory adrs to CPU (60x bus) adrs */
#define PCI_IO2LOCAL(x) \
    (uint32_t)(((VUINT32)x  - PCI_IO_ADRS) + CPU_PCI_IO_ADRS)

#define PCI_MEM2LOCAL(x) \
    (uint32_t)(((VUINT32)x  - PCI_MEM_ADRS) + CPU_PCI_MEM_ADRS)


/* 60x bus adrs to PCI (non-prefetchable) memory address */

#define LOCAL2PCI_MEMIO(x) \
     (uint32_t)((VUINT32)(x) + PCI_MSTR_MEM_BUS)


/* PCI defines begin */

#define PCI_BRIDGE_INTR_CTL_BA      0x4730000
#define PCI_BRIDGE_INTR_CTL_SIZE    0x10000

#define PCI_AGENT_IMMR_BA   0x4800000
#define PCI_AGENT_IMMR_SIZE 0x10000


#define PCI_CFG_ADR_REG  0x10900
#define PCI_CFG_DATA_REG 0x10904
#define PCI_AUTO_CONFIG_ADRS  0x4c00

#define PPCACR_PRKM_MASK 0XF0
#define PCI_REQUEST_LEVEL 0x3

#define CLASS_OFFSET      0xB
#define CLASS_WIDTH       0x1
#define BRIDGE_CLASS_TYPE 0x6


#define PCICMD_ADRS     (PCI_CFG_BASE + 0x04)  /* PCI cmd reg */
#define PCICMD_VAL      0x00000006             /* PCI COMMAND Default value */
#define PCISTAT_ADRS    (PCI_CFG_BASE + 0x06)  /* PCI status reg */

#define NUM_PCI_SLOTS		0x3          /* 3 PCI slots: 0 to 2 */

#define PCI_XINT1_LVL		0x0          /* PCI XINT1 routed to IRQ0  */
#define PCI_XINT2_LVL		0x1          /* PCI XINT2 routed to IRQ1 */
#define PCI_XINT3_LVL		0x2          /* PCI XINT3 routed to IRQ2 */

#define PCI_SLOT1_DEVNO		0x16         /* PCI SLOT 1 Device no */
#define PCI_LAT_TIMER		0x40         /* latency timer value, 64 PCI clocks */

#define PCI1_DEV_ID			0x826010E3
#define PCI2_DEV_ID			0x826110E3
#define PCI3_DEV_ID			0x826210E3
#define PCI_DEV_ID_8266		0x18C11057   /* Vendor & Dev Id for MPC8266ADS-PCI board */
#define PCI_ID_I82559		0x12298086   /* Id for Intel 82559 */
#define PCI_ID_I82559ER		0x12098086   /* Id for Intel 82559 ER */
#define PCI_ID_I82559_IB	0x10308086   /* Id for In-business card */

#define MPC8266ADS_PCI_IRQ       19

#define PCI_INTA_IRQ     MPC8266ADS_PCI_IRQ
#define PCI_INTB_IRQ     MPC8266ADS_PCI_IRQ
#define PCI_INTC_IRQ     MPC8266ADS_PCI_IRQ

#define PCI_ADDRESS_REGISTER    0x30000290     /* PCI Address Register */
#define PCI_DATA_REGISTER       0x30000294     /* PCI Data Register */

#define PCI_SIZE_MASK_4K   0xfffff
#define PCI_SIZE_MASK_8K   0xffffe
#define PCI_SIZE_MASK_16K  0xffffc
#define PCI_SIZE_MASK_32K  0xffff8
#define PCI_SIZE_MASK_64K  0xffff0
#define PCI_SIZE_MASK_128K 0xfffe0
#define PCI_SIZE_MASK_256K 0xfffc0
#define PCI_SIZE_MASK_512K 0xfff80
#define PCI_SIZE_MASK_1M   0xfff00
#define PCI_SIZE_MASK_2M   0xffe00
#define PCI_SIZE_MASK_4M   0xffc00
#define PCI_SIZE_MASK_8M   0xff800
#define PCI_SIZE_MASK_16M  0xff000
#define PCI_SIZE_MASK_32M  0xfe000
#define PCI_SIZE_MASK_64M  0xfc000
#define PCI_SIZE_MASK_128M 0xf8000
#define PCI_SIZE_MASK_256M 0xe0000
#define PCI_SIZE_MASK_512M 0xc0000
#define PCI_SIZE_MASK_1G   0x80000
#define PCI_SIZE_MASK_2G   0x00000


#define DELTA(a,b)		(sysAbs((int)a - (int)b))

#define BUS	0				/* bus-less board */

#undef  CPU
#define CPU	PPC603				/* CPU type */

#define N_SIO_CHANNELS	 	2		/* No. serial I/O channels */


/* define the decrementer input clock frequency */

#define DEC_CLOCK_FREQ	OSCILLATOR_FREQ

/*
 * Internal Memory Map base Address calculation
 *
 * If config.h has IMMAP_REMAP defined, then the internal mamory map
 * is defined to be 0x04700000, as defined in the ADS8266-PCI manual.
 *
 * Otherwise the memory map is defined by the Hard Reset Configuration Word
 * and must be determined by looking at bits 13:15 of the configuration word.
 * Bits 13:15 are bits 5:7 of the second byte of the config word: HRCW_BYTE_1
 */

#if 0
#if   ((HRCW_BYTE_1 & 0x07) == 0)
#	define	RST_INTERNAL_MEM_MAP_ADDR	0x00000000
#elif ((HRCW_BYTE_1 & 0x07) == 1)
#	define	RST_INTERNAL_MEM_MAP_ADDR	0x00F00000
#elif ((HRCW_BYTE_1 & 0x07) == 2)
#	define	RST_INTERNAL_MEM_MAP_ADDR	0x0F000000
#elif ((HRCW_BYTE_1 & 0x07) == 3)
#	define	RST_INTERNAL_MEM_MAP_ADDR	0x0FF00000
#elif ((HRCW_BYTE_1 & 0x07) == 4)
#	define	RST_INTERNAL_MEM_MAP_ADDR	0xF0000000
#elif ((HRCW_BYTE_1 & 0x07) == 5)
#	define	RST_INTERNAL_MEM_MAP_ADDR	0xF0F00000
#elif ((HRCW_BYTE_1 & 0x07) == 6)
#	define	RST_INTERNAL_MEM_MAP_ADDR	0xFF000000
#elif ((HRCW_BYTE_1 & 0x07) == 7)
#	define	RST_INTERNAL_MEM_MAP_ADDR	0xFFF00000
#endif
#endif

#if defined (IMMAP_REMAP)
#	define INTERNAL_MEM_MAP_ADDR	0x0F000000	/* defined by bsp */
#else
#	define INTERNAL_MEM_MAP_ADDR	RST_INTERNAL_MEM_MAP_ADDR
#endif

#define PQII_REG_BASE_OFF		0x10000
#define PQII_REG_BASE			(INTERNAL_MEM_MAP_ADDR + PQII_REG_BASE_OFF)
#define INTERNAL_MEM_MAP_SIZE	0x00020000	/* 128 K bytes */
#define IMMR_OFFSET				0x01a8		/* offset from SIU base */
#define IMMR_ISB_MASK			0xfffe0000	/* Internal Space Base mask */
#define IMMR_PARTNUM_MASK		0x0000ff00	/* Part Number mask */
#define IMMR_MASKNUM_MASK		0x000000ff	/* Mask Number mask */
#define DPRAM1_SIZE				0x00004000	/* 16K bytes of DPRAM in bank 1 */

/* Security IMMR registers . Initialised in romInit.s */
#define M82XX_SECBR(base) (CAST(VUINT32 *)((base) + 0x101B4)) 
#define M82XX_SECMR(base) (CAST(VUINT32 *)((base) + 0x101BC))

#define SEC_ENG_BASE_ADRS (INTERNAL_MEM_MAP_ADDR + 0x40000)
#define SEC_ENG_SIZE      0x20000
#define SEC_ENG_SIZE_MASK 0xfffe0000

/* CPU type in the PVR */

#define CPU_TYPE_8260			0xAAAA		/* value for PPC8260 */
#define CPU_TYPE_8266			0xBBBB		/* value for PPC8266 */
#define	CPU_REV_A1_MASK_NUM		0x0010		/* revision mask num */
#define HIP4_ID			       	0x80810000  /* device ID via PVR */
#define HIP4_MASK	       		0xFFFF0000  /* mask upper word   */
#define HIP7_ID				0x80820000

/*
 * Maximum SCC Number used.
*/
#define MAX_SCC_SIO_CHANS 4

/*
 * CPM Parameter RAM definitions.  From Table 13-10, page 13-18 in
 *  MPC8260 PowerQUICC-II User's Manual
 */
#define SCC1_PRAM	(INTERNAL_MEM_MAP_ADDR + 0x8000)
#define SCC2_PRAM	(INTERNAL_MEM_MAP_ADDR + 0x8100)
#define SCC3_PRAM	(INTERNAL_MEM_MAP_ADDR + 0x8200)
#define SCC4_PRAM	(INTERNAL_MEM_MAP_ADDR + 0x8300)
#define FCC1_PRAM	(INTERNAL_MEM_MAP_ADDR + 0x8400)
#define FCC2_PRAM	(INTERNAL_MEM_MAP_ADDR + 0x8500)
#define FCC3_PRAM	(INTERNAL_MEM_MAP_ADDR + 0x8600)
#define MCC1_PRAM	(INTERNAL_MEM_MAP_ADDR + 0x8700)
#define SMC1_BASE	(INTERNAL_MEM_MAP_ADDR + 0x87FC)
#define IDMA1_BASE	(INTERNAL_MEM_MAP_ADDR + 0x87FE)
#define MCC2_PRAM	(INTERNAL_MEM_MAP_ADDR + 0x8800)
#define SMC2_BASE	(INTERNAL_MEM_MAP_ADDR + 0x88FC)
#define IDMA2_BASE	(INTERNAL_MEM_MAP_ADDR + 0x88FE)
#define SPI_BASE	(INTERNAL_MEM_MAP_ADDR + 0x89FC)
#define IDMA3_BASE	(INTERNAL_MEM_MAP_ADDR + 0x89FE)
#define RISC_TMR	(INTERNAL_MEM_MAP_ADDR + 0x8AE0)
#define REV_NUM		(INTERNAL_MEM_MAP_ADDR + 0x8AF0)
#define RAND		(INTERNAL_MEM_MAP_ADDR + 0x8AF8)
#define I2C_BASE	(INTERNAL_MEM_MAP_ADDR + 0x8AFC)
#define IDMA4_BASE	(INTERNAL_MEM_MAP_ADDR + 0x8AFE)

/*
* Dual Ported RAM definitions
*
* This is the area where Buffer Descriptor tables are setup for all the
* CPM controlled devices.  This bsp defines areas for the SCC's, IDMA's
* and the I2C controllers.  The FCC DPRAM areas are defined in the FCC
* driver code, and start at INTERNAL_MEM_MAP_ADDR + 0x8400
*/
#define I2C_PARAM_OFF	0x200	/* offset from IMM */

/* Add in IDMA registers for PCI bridge register read errata fix*/

#define IDSR1   		(PQII_REG_BASE | 0x1020)
#define IDMR1   		(PQII_REG_BASE | 0x1024)
#define IDSR2   		(PQII_REG_BASE | 0x1028)
#define IDMR2   		(PQII_REG_BASE | 0x102c)
#define IDSR3   		(PQII_REG_BASE | 0x1030)
#define IDMR3   		(PQII_REG_BASE | 0x1034)
#define IDSR4   		(PQII_REG_BASE | 0x1038)
#define IDMR5   		(PQII_REG_BASE | 0x103c)

/* I2C register and buffer definitions */

#define I2C_MAX_RXDATA		32		/* limit receives to 32 bytes */
#define I2C_MAX_TXDATA		32		/* limit transmits to 32 bytes */
#define I2C_MAX_CLK			70000	/* limit max data rate to 70Kbps */
#define I2C_FUNC_CODE		0x10	/* no snooping, big-endian, 60x bus */
#define I2C_RDYLST_TXBD		0x8C00  /* full, last data, start, interrupt */
#define I2C_RDY_TXBD		0x8400  /* full, start, interrupt */
#define I2C_INIT_RXBD		0xA000  /* empty, Last BD */
#define I2C_BD_CPMOWN		0x8000  /* cpm owns this BD */
#define I2C_MASTER_ADDR		0x55	/* some default address */
#define I2C_DRAM_ADDR		(0x50 | I2C_SW2_SETTING)	  /* SDRAM DIMM 7 bit addr */
#define I2C_READ			1
#define I2C_WRITE			0
#define I2C_BD_WRAP			0x2000	/* buffer desc table wrap */
#define I2C_GEN_INT			0x1000  /* set interrupt bits in event register */

#define	I2C_MOD	(uint8_t *)(INTERNAL_MEM_MAP_ADDR + 0x11860)	/* mode register */
#	define	REVD	0x20	/* Reverse Data */
#	define	GCD		0x10	/* General Call Disable */
#	define	FLT		0x08	/* Clock Filter */
#	define	PDIV32	0x00	/* predivide by 32 */
#	define	PDIV16	0x02	/* predivide by 16 */
#	define	PDIV8	0x04	/* predivide by  8 */
#	define	PDIV4	0x06	/* predivide by  4 */
#	define	I2C_EN 	0x01	/* enable I2C */
#define	I2C_ADD	(uint8_t *)(INTERNAL_MEM_MAP_ADDR + 0x11864)	/* address reg */
#define	I2C_BRG	(uint8_t *)(INTERNAL_MEM_MAP_ADDR + 0x11868)	/* baud rate reg */
#	define	DIV		6		/* always use this divisor */
#define	I2C_COM	(uint8_t *)(INTERNAL_MEM_MAP_ADDR + 0x1186C)	/* command reg */
#	define I2C_MASTER 	0x01
#	define I2C_TRANSMIT 0x80
#define	I2C_ER	(uint8_t *)(INTERNAL_MEM_MAP_ADDR + 0x11870)	/* event reg */
#define	I2C_MR	(uint8_t *)(INTERNAL_MEM_MAP_ADDR + 0x11874)	/* event mask reg */
#	define I2C_TXE	0x10				/* TX Error, set when an error */
#	define I2C_BSY	0x04				/* Busy, set after rx overrun */
#	define I2C_TXB	0x02				/* TX buffer empty */
#	define I2C_RXB	0x01				/* RX buffer available */
#	define I2C_ERR  (I2C_TXE + I2C_BSY)	/* any I2C error */


/* The parallel port needs some setup for I2C to work
* in particular Bits 14 and 15 of the parallel port D registers need to
* be setup.
*/
#define BIT14		0x0002	/* for word access to PPxx ports */
#define BIT15		0x0001	/* for word access to PPxx ports */

#define PODRD		(INTERNAL_MEM_MAP_ADDR + 0x10D6C)
#define PDIRD		(INTERNAL_MEM_MAP_ADDR + 0x10D60)
#define PPARD		(INTERNAL_MEM_MAP_ADDR + 0x10D64)
#define PSORD		(INTERNAL_MEM_MAP_ADDR + 0x10D68)


#define DCM_DUAL_ADDR 		0x0000
#define DCM_SINGLE_ADDR 	0x1000
#define DCM_TRANS_BUF_64 	0x0000
#define DCM_TRANS_BUF_128 	0x0040
#define DCM_TRANS_BUF_256	0x0080
#define DCM_TRANS_BUF_512	0x00c0
#define DCM_TRANS_BUF_1024	0x0100
#define DCM_TRANS_BUF_2048	0x0180
#define DCM_EXT_REQ			0x0008
#define DCM_MEM_MEM			0x0000
#define DCM_PER_MEM			0x0002
#define DCM_MEM_PER			0x0001
#define DCM_TC2				0x0400
#define DCM_DONE			0x0004