flip_latch.tan.qmsg

频率计

{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "Q0\[3\]~reg0 A0\[3\] clk 2.900 ns register " "Info: tsu for register \"Q0\[3\]~reg0\" (data pin = \"A0\[3\]\", clock pin = \"clk\") is 2.900 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.900 ns + Longest pin register " "Info: + Longest pin to register delay is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns A0\[3\] 1 PIN PIN_84 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_84; Fanout = 1; PIN Node = 'A0\[3\]'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "" { A0[3] } "NODE_NAME" } "" } } { "flip_latch.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/flip_latch.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.600 ns) 3.900 ns Q0\[3\]~reg0 2 REG LC1 1 " "Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC1; Fanout = 1; REG Node = 'Q0\[3\]~reg0'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "3.700 ns" { A0[3] Q0[3]~reg0 } "NODE_NAME" } "" } } { "flip_latch.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/flip_latch.v" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 71.79 % " "Info: Total cell delay = 2.800 ns ( 71.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 28.21 % " "Info: Total interconnect delay = 1.100 ns ( 28.21 % )" {  } {  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "3.900 ns" { A0[3] Q0[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { A0[3] A0[3]~out Q0[3]~reg0 } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "flip_latch.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/flip_latch.v" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.800 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_87 24 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 24; CLK Node = 'clk'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "" { clk } "NODE_NAME" } "" } } { "flip_latch.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/flip_latch.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns Q0\[3\]~reg0 2 REG LC1 1 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC1; Fanout = 1; REG Node = 'Q0\[3\]~reg0'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "0.500 ns" { clk Q0[3]~reg0 } "NODE_NAME" } "" } } { "flip_latch.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/flip_latch.v" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "1.800 ns" { clk Q0[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { clk clk~out Q0[3]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "3.900 ns" { A0[3] Q0[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { A0[3] A0[3]~out Q0[3]~reg0 } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.600ns } } } { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "1.800 ns" { clk Q0[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { clk clk~out Q0[3]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Q5\[0\] Q5\[0\]~reg0 3.200 ns register " "Info: tco from clock \"clk\" to destination pin \"Q5\[0\]\" through register \"Q5\[0\]~reg0\" is 3.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.800 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_87 24 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 24; CLK Node = 'clk'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "" { clk } "NODE_NAME" } "" } } { "flip_latch.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/flip_latch.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns Q5\[0\]~reg0 2 REG LC17 1 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC17; Fanout = 1; REG Node = 'Q5\[0\]~reg0'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "0.500 ns" { clk Q5[0]~reg0 } "NODE_NAME" } "" } } { "flip_latch.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/flip_latch.v" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "1.800 ns" { clk Q5[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { clk clk~out Q5[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" {  } { { "flip_latch.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/flip_latch.v" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.200 ns + Longest register pin " "Info: + Longest register to pin delay is 0.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q5\[0\]~reg0 1 REG LC17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 1; REG Node = 'Q5\[0\]~reg0'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "" { Q5[0]~reg0 } "NODE_NAME" } "" } } { "flip_latch.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/flip_latch.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Q5\[0\] 2 PIN PIN_37 0 " "Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_37; Fanout = 0; PIN Node = 'Q5\[0\]'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "0.200 ns" { Q5[0]~reg0 Q5[0] } "NODE_NAME" } "" } } { "flip_latch.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/flip_latch.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.200 ns 100.00 % " "Info: Total cell delay = 0.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "0.200 ns" { Q5[0]~reg0 Q5[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { Q5[0]~reg0 Q5[0] } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "1.800 ns" { clk Q5[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { clk clk~out Q5[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "0.200 ns" { Q5[0]~reg0 Q5[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { Q5[0]~reg0 Q5[0] } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "Q0\[3\]~reg0 A0\[3\] clk -0.400 ns register " "Info: th for register \"Q0\[3\]~reg0\" (data pin = \"A0\[3\]\", clock pin = \"clk\") is -0.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.800 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_87 24 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 24; CLK Node = 'clk'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "" { clk } "NODE_NAME" } "" } } { "flip_latch.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/flip_latch.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns Q0\[3\]~reg0 2 REG LC1 1 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC1; Fanout = 1; REG Node = 'Q0\[3\]~reg0'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "0.500 ns" { clk Q0[3]~reg0 } "NODE_NAME" } "" } } { "flip_latch.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/flip_latch.v" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "1.800 ns" { clk Q0[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { clk clk~out Q0[3]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "flip_latch.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/flip_latch.v" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns A0\[3\] 1 PIN PIN_84 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_84; Fanout = 1; PIN Node = 'A0\[3\]'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "" { A0[3] } "NODE_NAME" } "" } } { "flip_latch.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/flip_latch.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.600 ns) 3.900 ns Q0\[3\]~reg0 2 REG LC1 1 " "Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC1; Fanout = 1; REG Node = 'Q0\[3\]~reg0'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "3.700 ns" { A0[3] Q0[3]~reg0 } "NODE_NAME" } "" } } { "flip_latch.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/flip_latch.v" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 71.79 % " "Info: Total cell delay = 2.800 ns ( 71.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 28.21 % " "Info: Total interconnect delay = 1.100 ns ( 28.21 % )" {  } {  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "3.900 ns" { A0[3] Q0[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { A0[3] A0[3]~out Q0[3]~reg0 } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.600ns } } }  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "1.800 ns" { clk Q0[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { clk clk~out Q0[3]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch_cmp.qrpt" Compiler "flip_latch" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/db/flip_latch.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/flip_latch/" "" "3.900 ns" { A0[3] Q0[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { A0[3] A0[3]~out Q0[3]~reg0 } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.600ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 10 20:57:09 2006 " "Info: Processing ended: Mon Jul 10 20:57:09 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}