📄 dispdecoder.fit.rpt
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; I/O Standard ; Load ; Termination Resistance ;
+--------------+-------+------------------------+
; LVTTL ; 10 pF ; Not Available ;
; LVCMOS ; 10 pF ; Not Available ;
; TTL ; 0 pF ; Not Available ;
+--------------+-------+------------------------+
+----------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |dispdecoder ; 10 ; 47 ; |dispdecoder ;
+----------------------------+------------+------+---------------------+
+---------------------------------+
; Non-Global High Fan-Out Signals ;
+----------------------+----------+
; Name ; Fan-Out ;
+----------------------+----------+
; data_in[1] ; 14 ;
; data_in[2] ; 14 ;
; data_in[0] ; 12 ;
; data_in[3] ; 7 ;
; hide~363 ; 7 ;
; reduce_or~1092 ; 3 ;
; reduce_or~1091 ; 3 ;
; dp_s100hz ; 2 ;
; dp_s10hz ; 2 ;
; disp_select[0] ; 2 ;
; disp_select[1] ; 2 ;
; disp_select[2] ; 2 ;
; reduce_or~1052sexp2 ; 2 ;
; reduce_or~1054sexp2 ; 2 ;
; data_out[0]$latch~10 ; 2 ;
; data_out[1]$latch~10 ; 2 ;
; data_out[2]$latch~10 ; 2 ;
; data_out[3]$latch~10 ; 2 ;
; data_out[4]$latch~10 ; 2 ;
; data_out[5]$latch~10 ; 2 ;
; data_out[6]$latch~10 ; 2 ;
; reduce_or~1093 ; 1 ;
; counter_out ; 1 ;
; Q1[0] ; 1 ;
; Q1[1] ; 1 ;
; Q1[2] ; 1 ;
; Q1[3] ; 1 ;
; Q2[0] ; 1 ;
; Q2[1] ; 1 ;
; Q2[2] ; 1 ;
; Q2[3] ; 1 ;
; Q3[0] ; 1 ;
; Q3[1] ; 1 ;
; Q3[2] ; 1 ;
; Q3[3] ; 1 ;
; Q4[0] ; 1 ;
; Q4[1] ; 1 ;
; Q4[2] ; 1 ;
; Q4[3] ; 1 ;
; Q5[0] ; 1 ;
; Q5[1] ; 1 ;
; Q5[2] ; 1 ;
; Q5[3] ; 1 ;
; dp_s1hz ; 1 ;
; reduce_or~1053sexp5 ; 1 ;
; reduce_or~1053sexp2 ; 1 ;
; reduce_or~1051sexp4 ; 1 ;
; reduce_or~1051sexp3 ; 1 ;
; reduce_or~1050sexp4 ; 1 ;
; reduce_or~1050sexp3 ; 1 ;
+----------------------+----------+
+------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+-------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 50 / 144 ( 34 % ) ;
+----------------------------+-------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 2.50) ; Number of LABs (Total = 3) ;
+----------------------------------------+-----------------------------+
; 0 ; 1 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 1 ;
+----------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 4.00) ; Number of LABs (Total = 2) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 2 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+-------------------------------------------------+-----------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC1 ; dp_s10hz, disp_select[1], disp_select[2], disp_select[0], dp_s1hz, dp_s100hz ; dp ;
; A ; LC9 ; data_in[2], data_in[1], data_in[3], data_in[0] ; data_out[0]$latch~10 ;
; A ; LC2 ; hide~363, data_out[6]$latch~10, reduce_or~1054sexp2, reduce_or~1052sexp2, reduce_or~1050sexp3, reduce_or~1050sexp4 ; data_out[6]$latch~10, data_out[6] ;
; A ; LC3 ; hide~363, data_out[5]$latch~10, reduce_or~1054sexp2, reduce_or~1052sexp2, reduce_or~1051sexp3, reduce_or~1051sexp4 ; data_out[5]$latch~10, data_out[5] ;
; A ; LC4 ; reduce_or~1056, hide~363, data_out[0]$latch~10 ; data_out[0]$latch~10, data_out[0] ;
; B ; LC17 ; hide~363, data_out[4]$latch~10, reduce_or~1091, reduce_or~1092, reduce_or~1052sexp3 ; data_out[4]$latch~10, data_out[4] ;
; B ; LC18 ; hide~363, data_out[3]$latch~10, reduce_or~1091, reduce_or~1053sexp2, reduce_or~1093, reduce_or~1092, reduce_or~1053sexp5 ; data_out[3]$latch~10, data_out[3] ;
; B ; LC19 ; hide~363, data_out[2]$latch~10, reduce_or~1091, reduce_or~1054sexp3, data_in[0] ; data_out[2]$latch~10, data_out[2] ;
; B ; LC20 ; hide~363, data_out[1]$latch~10, reduce_or~1055sexp1, reduce_or~1092, reduce_or~1055sexp3, reduce_or~1055sexp4 ; data_out[1]$latch~10, data_out[1] ;
; C ; LC34 ; disp_select[2], disp_select[1], disp_select[0], counter_out, Q5[3], Q5[2], Q5[1], Q5[0], dp_s100hz, Q4[3], Q4[2], Q4[1], Q4[0], Q3[3], Q3[2], Q3[1], Q3[0], dp_s10hz, Q2[0], Q2[1], Q2[2], Q2[3], Q1[3], Q1[2], Q1[1], Q1[0] ; data_out[6]$latch~10, data_out[5]$latch~10, data_out[4]$latch~10, data_out[3]$latch~10, data_out[2]$latch~10, data_out[1]$latch~10, data_out[0]$latch~10 ;
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Mon Jul 17 22:27:24 2006
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off dispdecoder -c dispdecoder
Info: Automatically selected device EPM7064STC100-5 for design dispdecoder
Info: Fitting design with smaller device may be possible, but smaller device must be specified
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Mon Jul 17 22:27:25 2006
Info: Elapsed time: 00:00:02
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