gate_control.tan.qmsg

频率计

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW1 register wire_1 register wire_2 48.54 MHz 20.6 ns Internal " "Info: Clock \"SW1\" has Internal fmax of 48.54 MHz between source register \"wire_1\" and destination register \"wire_2\" (period= 20.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wire_1 1 REG LC1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { wire_1 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns wire_2 2 REG LC15 2 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC15; Fanout = 2; REG Node = 'wire_2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns ( 72.22 % ) " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 27.78 % ) " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 {} wire_2 {} } { 0.000ns 1.000ns } { 0.000ns 2.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.600 ns - Smallest " "Info: - Smallest clock skew is -4.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 8.500 ns + Shortest register " "Info: + Shortest clock path from clock \"SW1\" to destination register is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW1 1 CLK PIN_33 12 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_33; Fanout = 12; CLK Node = 'SW1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW1 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 4.800 ns fref~104 2 COMB LOOP LC8 4 " "Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'" { { "Info" "ITDB_PART_OF_SCC" "fref~104 LC8 " "Info: Loc. = LC8; Node \"fref~104\"" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fref~104 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fref~104 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { SW1 fref~104 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 8.500 ns wire_2 3 REG LC15 2 " "Info: 3: + IC(1.000 ns) + CELL(2.700 ns) = 8.500 ns; Loc. = LC15; Fanout = 2; REG Node = 'wire_2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { fref~104 wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns ( 88.24 % ) " "Info: Total cell delay = 7.500 ns ( 88.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 11.76 % ) " "Info: Total interconnect delay = 1.000 ns ( 11.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.500 ns" { SW1 fref~104 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.500 ns" { SW1 {} SW1~out {} fref~104 {} wire_2 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 source 13.100 ns - Longest register " "Info: - Longest clock path from clock \"SW1\" to source register is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW1 1 CLK PIN_33 12 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_33; Fanout = 12; CLK Node = 'SW1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW1 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~94 2 COMB LC4 3 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 3; COMB Node = 'fref~94'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { SW1 fref~94 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.400 ns fref~104 3 COMB LOOP LC8 4 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'" { { "Info" "ITDB_PART_OF_SCC" "fref~104 LC8 " "Info: Loc. = LC8; Node \"fref~104\"" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fref~104 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fref~104 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { fref~94 fref~104 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 13.100 ns wire_1 4 REG LC1 5 " "Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { fref~104 wire_1 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.100 ns ( 84.73 % ) " "Info: Total cell delay = 11.100 ns ( 84.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 15.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 15.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { SW1 fref~94 fref~104 wire_1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { SW1 {} SW1~out {} fref~94 {} fref~104 {} wire_1 {} } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.500 ns" { SW1 fref~104 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.500 ns" { SW1 {} SW1~out {} fref~104 {} wire_2 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { SW1 fref~94 fref~104 wire_1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { SW1 {} SW1~out {} fref~94 {} fref~104 {} wire_1 {} } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 55 -1 0 } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 21 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 {} wire_2 {} } { 0.000ns 1.000ns } { 0.000ns 2.600ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.500 ns" { SW1 fref~104 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.500 ns" { SW1 {} SW1~out {} fref~104 {} wire_2 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { SW1 fref~94 fref~104 wire_1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { SW1 {} SW1~out {} fref~94 {} fref~104 {} wire_1 {} } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW2 register wire_1 register wire_2 48.54 MHz 20.6 ns Internal " "Info: Clock \"SW2\" has Internal fmax of 48.54 MHz between source register \"wire_1\" and destination register \"wire_2\" (period= 20.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wire_1 1 REG LC1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { wire_1 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns wire_2 2 REG LC15 2 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC15; Fanout = 2; REG Node = 'wire_2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns ( 72.22 % ) " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 27.78 % ) " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 {} wire_2 {} } { 0.000ns 1.000ns } { 0.000ns 2.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.600 ns - Smallest " "Info: - Smallest clock skew is -4.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 destination 8.500 ns + Shortest register " "Info: + Shortest clock path from clock \"SW2\" to destination register is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW2 1 CLK PIN_36 14 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_36; Fanout = 14; CLK Node = 'SW2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW2 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 4.800 ns fref~104 2 COMB LOOP LC8 4 " "Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'" { { "Info" "ITDB_PART_OF_SCC" "fref~104 LC8 " "Info: Loc. = LC8; Node \"fref~104\"" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fref~104 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fref~104 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { SW2 fref~104 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 8.500 ns wire_2 3 REG LC15 2 " "Info: 3: + IC(1.000 ns) + CELL(2.700 ns) = 8.500 ns; Loc. = LC15; Fanout = 2; REG Node = 'wire_2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { fref~104 wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns ( 88.24 % ) " "Info: Total cell delay = 7.500 ns ( 88.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 11.76 % ) " "Info: Total interconnect delay = 1.000 ns ( 11.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.500 ns" { SW2 fref~104 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.500 ns" { SW2 {} SW2~out {} fref~104 {} wire_2 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 source 13.100 ns - Longest register " "Info: - Longest clock path from clock \"SW2\" to source register is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW2 1 CLK PIN_36 14 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_36; Fanout = 14; CLK Node = 'SW2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW2 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~94 2 COMB LC4 3 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 3; COMB Node = 'fref~94'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { SW2 fref~94 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.400 ns fref~104 3 COMB LOOP LC8 4 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'" { { "Info" "ITDB_PART_OF_SCC" "fref~104 LC8 " "Info: Loc. = LC8; Node \"fref~104\"" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fref~104 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fref~104 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { fref~94 fref~104 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 13.100 ns wire_1 4 REG LC1 5 " "Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { fref~104 wire_1 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.100 ns ( 84.73 % ) " "Info: Total cell delay = 11.100 ns ( 84.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 15.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 15.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { SW2 fref~94 fref~104 wire_1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { SW2 {} SW2~out {} fref~94 {} fref~104 {} wire_1 {} } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.500 ns" { SW2 fref~104 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.500 ns" { SW2 {} SW2~out {} fref~104 {} wire_2 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { SW2 fref~94 fref~104 wire_1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { SW2 {} SW2~out {} fref~94 {} fref~104 {} wire_1 {} } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 55 -1 0 } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 21 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 {} wire_2 {} } { 0.000ns 1.000ns } { 0.000ns 2.600ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.500 ns" { SW2 fref~104 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.500 ns" { SW2 {} SW2~out {} fref~104 {} wire_2 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { SW2 fref~94 fref~104 wire_1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { SW2 {} SW2~out {} fref~94 {} fref~104 {} wire_1 {} } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "f10hz register wire_1 register wire_2 87.72 MHz 11.4 ns Internal " "Info: Clock \"f10hz\" has Internal fmax of 87.72 MHz between source register \"wire_1\" and destination register \"wire_2\" (period= 11.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wire_1 1 REG LC1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { wire_1 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns wire_2 2 REG LC15 2 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC15; Fanout = 2; REG Node = 'wire_2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns ( 72.22 % ) " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 27.78 % ) " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 {} wire_2 {} } { 0.000ns 1.000ns } { 0.000ns 2.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f10hz destination 13.100 ns + Shortest register " "Info: + Shortest clock path from clock \"f10hz\" to destination register is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns f10hz 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'f10hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { f10hz } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~94 2 COMB LC4 3 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 3; COMB Node = 'fref~94'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { f10hz fref~94 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.400 ns fref~104 3 COMB LOOP LC8 4 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'" { { "Info" "ITDB_PART_OF_SCC" "fref~104 LC8 " "Info: Loc. = LC8; Node \"fref~104\"" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fref~104 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fref~104 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { fref~94 fref~104 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 13.100 ns wire_2 4 REG LC15 2 " "Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC15; Fanout = 2; REG Node = 'wire_2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { fref~104 wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.100 ns ( 84.73 % ) " "Info: Total cell delay = 11.100 ns ( 84.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 15.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 15.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { f10hz fref~94 fref~104 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { f10hz {} f10hz~out {} fref~94 {} fref~104 {} wire_2 {} } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f10hz source 13.100 ns - Longest register " "Info: - Longest clock path from clock \"f10hz\" to source register is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns f10hz 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'f10hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { f10hz } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~94 2 COMB LC4 3 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 3; COMB Node = 'fref~94'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { f10hz fref~94 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.400 ns fref~104 3 COMB LOOP LC8 4 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'" { { "Info" "ITDB_PART_OF_SCC" "fref~104 LC8 " "Info: Loc. = LC8; Node \"fref~104\"" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fref~104 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fref~104 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { fref~94 fref~104 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 13.100 ns wire_1 4 REG LC1 5 " "Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { fref~104 wire_1 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.100 ns ( 84.73 % ) " "Info: Total cell delay = 11.100 ns ( 84.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 15.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 15.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { f10hz fref~94 fref~104 wire_1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { f10hz {} f10hz~out {} fref~94 {} fref~104 {} wire_1 {} } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { f10hz fref~94 fref~104 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { f10hz {} f10hz~out {} fref~94 {} fref~104 {} wire_2 {} } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { f10hz fref~94 fref~104 wire_1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { f10hz {} f10hz~out {} fref~94 {} fref~104 {} wire_1 {} } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 55 -1 0 } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 21 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 {} wire_2 {} } { 0.000ns 1.000ns } { 0.000ns 2.600ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { f10hz fref~94 fref~104 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { f10hz {} f10hz~out {} fref~94 {} fref~104 {} wire_2 {} } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { f10hz fref~94 fref~104 wire_1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { f10hz {} f10hz~out {} fref~94 {} fref~104 {} wire_1 {} } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "f100hz register wire_1 register wire_2 87.72 MHz 11.4 ns Internal " "Info: Clock \"f100hz\" has Internal fmax of 87.72 MHz between source register \"wire_1\" and destination register \"wire_2\" (period= 11.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wire_1 1 REG LC1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { wire_1 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns wire_2 2 REG LC15 2 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC15; Fanout = 2; REG Node = 'wire_2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns ( 72.22 % ) " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 27.78 % ) " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 {} wire_2 {} } { 0.000ns 1.000ns } { 0.000ns 2.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f100hz destination 13.100 ns + Shortest register " "Info: + Shortest clock path from clock \"f100hz\" to destination register is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns f100hz 1 CLK PIN_20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_20; Fanout = 1; CLK Node = 'f100hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { f100hz } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~94 2 COMB LC4 3 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 3; COMB Node = 'fref~94'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { f100hz fref~94 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.400 ns fref~104 3 COMB LOOP LC8 4 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'" { { "Info" "ITDB_PART_OF_SCC" "fref~104 LC8 " "Info: Loc. = LC8; Node \"fref~104\"" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fref~104 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fref~104 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { fref~94 fref~104 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 13.100 ns wire_2 4 REG LC15 2 " "Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC15; Fanout = 2; REG Node = 'wire_2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { fref~104 wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.100 ns ( 84.73 % ) " "Info: Total cell delay = 11.100 ns ( 84.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 15.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 15.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { f100hz fref~94 fref~104 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { f100hz {} f100hz~out {} fref~94 {} fref~104 {} wire_2 {} } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f100hz source 13.100 ns - Longest register " "Info: - Longest clock path from clock \"f100hz\" to source register is 13.100