gate_control.tan.qmsg

频率计

{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "fref~104 " "Warning: Node \"fref~104\"" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "f1hz " "Info: Assuming node \"f1hz\" is an undefined clock" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 15 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "f1hz" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW1 " "Info: Assuming node \"SW1\" is an undefined clock" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 14 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW2 " "Info: Assuming node \"SW2\" is an undefined clock" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 14 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "f10hz " "Info: Assuming node \"f10hz\" is an undefined clock" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 15 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "f10hz" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "f100hz " "Info: Assuming node \"f100hz\" is an undefined clock" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 15 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "f100hz" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW0 " "Info: Assuming node \"SW0\" is an undefined clock" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 14 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW0" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "dp_s1hz~13sexpand1 " "Info: Detected gated clock \"dp_s1hz~13sexpand1\" as buffer" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 12 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "dp_s1hz~13sexpand1" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "fref~104 " "Info: Detected gated clock \"fref~104\" as buffer" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "fref~104" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "fref~94 " "Info: Detected gated clock \"fref~94\" as buffer" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "fref~94" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "f1hz register wire_1 register wire_2 87.72 MHz 11.4 ns Internal " "Info: Clock \"f1hz\" has Internal fmax of 87.72 MHz between source register \"wire_1\" and destination register \"wire_2\" (period= 11.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wire_1 1 REG LC1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { wire_1 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns wire_2 2 REG LC15 2 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC15; Fanout = 2; REG Node = 'wire_2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns ( 72.22 % ) " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 27.78 % ) " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 {} wire_2 {} } { 0.000ns 1.000ns } { 0.000ns 2.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f1hz destination 13.100 ns + Shortest register " "Info: + Shortest clock path from clock \"f1hz\" to destination register is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns f1hz 1 CLK PIN_44 1 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_44; Fanout = 1; CLK Node = 'f1hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { f1hz } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.600 ns) 4.800 ns fref~94 2 COMB LC4 3 " "Info: 2: + IC(0.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 3; COMB Node = 'fref~94'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { f1hz fref~94 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.400 ns fref~104 3 COMB LOOP LC8 4 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'" { { "Info" "ITDB_PART_OF_SCC" "fref~104 LC8 " "Info: Loc. = LC8; Node \"fref~104\"" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fref~104 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fref~104 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { fref~94 fref~104 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 13.100 ns wire_2 4 REG LC15 2 " "Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC15; Fanout = 2; REG Node = 'wire_2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { fref~104 wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.100 ns ( 92.37 % ) " "Info: Total cell delay = 12.100 ns ( 92.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 7.63 % ) " "Info: Total interconnect delay = 1.000 ns ( 7.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { f1hz fref~94 fref~104 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { f1hz {} f1hz~out {} fref~94 {} fref~104 {} wire_2 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.200ns 3.600ns 4.600ns 2.700ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f1hz source 13.100 ns - Longest register " "Info: - Longest clock path from clock \"f1hz\" to source register is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns f1hz 1 CLK PIN_44 1 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_44; Fanout = 1; CLK Node = 'f1hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { f1hz } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.600 ns) 4.800 ns fref~94 2 COMB LC4 3 " "Info: 2: + IC(0.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 3; COMB Node = 'fref~94'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { f1hz fref~94 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.400 ns fref~104 3 COMB LOOP LC8 4 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'" { { "Info" "ITDB_PART_OF_SCC" "fref~104 LC8 " "Info: Loc. = LC8; Node \"fref~104\"" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fref~104 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fref~104 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { fref~94 fref~104 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 13.100 ns wire_1 4 REG LC1 5 " "Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { fref~104 wire_1 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.100 ns ( 92.37 % ) " "Info: Total cell delay = 12.100 ns ( 92.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 7.63 % ) " "Info: Total interconnect delay = 1.000 ns ( 7.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { f1hz fref~94 fref~104 wire_1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { f1hz {} f1hz~out {} fref~94 {} fref~104 {} wire_1 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.200ns 3.600ns 4.600ns 2.700ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { f1hz fref~94 fref~104 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { f1hz {} f1hz~out {} fref~94 {} fref~104 {} wire_2 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.200ns 3.600ns 4.600ns 2.700ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { f1hz fref~94 fref~104 wire_1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { f1hz {} f1hz~out {} fref~94 {} fref~104 {} wire_1 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.200ns 3.600ns 4.600ns 2.700ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 55 -1 0 } } { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 21 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 {} wire_2 {} } { 0.000ns 1.000ns } { 0.000ns 2.600ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { f1hz fref~94 fref~104 wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { f1hz {} f1hz~out {} fref~94 {} fref~104 {} wire_2 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.200ns 3.600ns 4.600ns 2.700ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { f1hz fref~94 fref~104 wire_1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { f1hz {} f1hz~out {} fref~94 {} fref~104 {} wire_1 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.200ns 3.600ns 4.600ns 2.700ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}