prev_cmp_gate_control.map.qmsg

来自「频率计」· QMSG 代码 · 共 8 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 21 18:12:41 2008 " "Info: Processing started: Mon Jul 21 18:12:41 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off gate_control -c gate_control " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gate_control -c gate_control" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\"; mismatched closing parenthesis  gate_control.v(67) " "Error (10170): Verilog HDL syntax error at gate_control.v(67) near text \")\"; mismatched closing parenthesis " {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 67 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "gate_control gate_control.v(1) " "Error (10112): Ignored design unit \"gate_control\" at gate_control.v(1) due to previous errors" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 1 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gate_control.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file gate_control.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "139 " "Info: Allocated 139 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Mon Jul 21 18:12:46 2008 " "Error: Processing ended: Mon Jul 21 18:12:46 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:05 " "Error: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}