gate_control.fnsim.qmsg

频率计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 21 18:23:32 2008 " "Info: Processing started: Mon Jul 21 18:23:32 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off gate_control -c gate_control --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gate_control -c gate_control --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gate_control.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file gate_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 gate_control " "Info: Found entity 1: gate_control" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "gate_control " "Info: Elaborating entity \"gate_control\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "fref gate_control.v(34) " "Warning (10240): Verilog HDL Always Construct warning at gate_control.v(34): inferring latch(es) for variable \"fref\", which holds its previous value in one or more paths through the always construct" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 34 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "dp_s1hz gate_control.v(34) " "Warning (10240): Verilog HDL Always Construct warning at gate_control.v(34): inferring latch(es) for variable \"dp_s1hz\", which holds its previous value in one or more paths through the always construct" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 34 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "dp_s10hz gate_control.v(34) " "Warning (10240): Verilog HDL Always Construct warning at gate_control.v(34): inferring latch(es) for variable \"dp_s10hz\", which holds its previous value in one or more paths through the always construct" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 34 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "dp_s100hz gate_control.v(34) " "Warning (10240): Verilog HDL Always Construct warning at gate_control.v(34): inferring latch(es) for variable \"dp_s100hz\", which holds its previous value in one or more paths through the always construct" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 34 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dp_s100hz gate_control.v(34) " "Info (10041): Inferred latch for \"dp_s100hz\" at gate_control.v(34)" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 34 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dp_s10hz gate_control.v(34) " "Info (10041): Inferred latch for \"dp_s10hz\" at gate_control.v(34)" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 34 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dp_s1hz gate_control.v(34) " "Info (10041): Inferred latch for \"dp_s1hz\" at gate_control.v(34)" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 34 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "fref gate_control.v(34) " "Info (10041): Inferred latch for \"fref\" at gate_control.v(34)" {  } { { "gate_control.v" "" { Text "R:/liu/gate_control/gate_control.v" 34 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 4 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Allocated 140 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 21 18:23:37 2008 " "Info: Processing ended: Mon Jul 21 18:23:37 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}