gate_control.tan.rpt

频率计

            Info: Total interconnect delay = 1.000 ns ( 11.76 % )
        Info: - Longest clock path from clock "SW2" to source register is 13.100 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_36; Fanout = 14; CLK Node = 'SW2'
            Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 3; COMB Node = 'fref~94'
            Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'
                Info: Loc. = LC8; Node "fref~104"
            Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'
            Info: Total cell delay = 11.100 ns ( 84.73 % )
            Info: Total interconnect delay = 2.000 ns ( 15.27 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Info: Clock "f10hz" has Internal fmax of 87.72 MHz between source register "wire_1" and destination register "wire_2" (period= 11.4 ns)
    Info: + Longest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC15; Fanout = 2; REG Node = 'wire_2'
        Info: Total cell delay = 2.600 ns ( 72.22 % )
        Info: Total interconnect delay = 1.000 ns ( 27.78 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "f10hz" to destination register is 13.100 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'f10hz'
            Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 3; COMB Node = 'fref~94'
            Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'
                Info: Loc. = LC8; Node "fref~104"
            Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC15; Fanout = 2; REG Node = 'wire_2'
            Info: Total cell delay = 11.100 ns ( 84.73 % )
            Info: Total interconnect delay = 2.000 ns ( 15.27 % )
        Info: - Longest clock path from clock "f10hz" to source register is 13.100 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'f10hz'
            Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 3; COMB Node = 'fref~94'
            Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'
                Info: Loc. = LC8; Node "fref~104"
            Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'
            Info: Total cell delay = 11.100 ns ( 84.73 % )
            Info: Total interconnect delay = 2.000 ns ( 15.27 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Info: Clock "f100hz" has Internal fmax of 87.72 MHz between source register "wire_1" and destination register "wire_2" (period= 11.4 ns)
    Info: + Longest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC15; Fanout = 2; REG Node = 'wire_2'
        Info: Total cell delay = 2.600 ns ( 72.22 % )
        Info: Total interconnect delay = 1.000 ns ( 27.78 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "f100hz" to destination register is 13.100 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_20; Fanout = 1; CLK Node = 'f100hz'
            Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 3; COMB Node = 'fref~94'
            Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'
                Info: Loc. = LC8; Node "fref~104"
            Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC15; Fanout = 2; REG Node = 'wire_2'
            Info: Total cell delay = 11.100 ns ( 84.73 % )
            Info: Total interconnect delay = 2.000 ns ( 15.27 % )
        Info: - Longest clock path from clock "f100hz" to source register is 13.100 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_20; Fanout = 1; CLK Node = 'f100hz'
            Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 3; COMB Node = 'fref~94'
            Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'
                Info: Loc. = LC8; Node "fref~104"
            Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'
            Info: Total cell delay = 11.100 ns ( 84.73 % )
            Info: Total interconnect delay = 2.000 ns ( 15.27 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Info: Clock "SW0" has Internal fmax of 56.82 MHz between source register "wire_1" and destination register "wire_2" (period= 17.6 ns)
    Info: + Longest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC15; Fanout = 2; REG Node = 'wire_2'
        Info: Total cell delay = 2.600 ns ( 72.22 % )
        Info: Total interconnect delay = 1.000 ns ( 27.78 % )
    Info: - Smallest clock skew is -3.100 ns
        Info: + Shortest clock path from clock "SW0" to destination register is 8.500 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_21; Fanout = 9; CLK Node = 'SW0'
            Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'
                Info: Loc. = LC8; Node "fref~104"
            Info: 3: + IC(1.000 ns) + CELL(2.700 ns) = 8.500 ns; Loc. = LC15; Fanout = 2; REG Node = 'wire_2'
            Info: Total cell delay = 7.500 ns ( 88.24 % )
            Info: Total interconnect delay = 1.000 ns ( 11.76 % )
        Info: - Longest clock path from clock "SW0" to source register is 11.600 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_21; Fanout = 9; CLK Node = 'SW0'
            Info: 2: + IC(1.000 ns) + CELL(3.100 ns) = 4.300 ns; Loc. = SEXP1; Fanout = 2; COMB Node = 'dp_s1hz~13sexpand1'
            Info: 3: + IC(0.000 ns) + CELL(3.600 ns) = 7.900 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'
                Info: Loc. = LC8; Node "fref~104"
            Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 11.600 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'
            Info: Total cell delay = 9.600 ns ( 82.76 % )
            Info: Total interconnect delay = 2.000 ns ( 17.24 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock "SW1" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "wire_1" and destination pin or register "wire_1" for clock "SW1" (Hold time is 1.4 ns)
    Info: + Largest clock skew is 4.600 ns
        Info: + Longest clock path from clock "SW1" to destination register is 13.100 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_33; Fanout = 12; CLK Node = 'SW1'
            Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 3; COMB Node = 'fref~94'
            Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'
                Info: Loc. = LC8; Node "fref~104"
            Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'
            Info: Total cell delay = 11.100 ns ( 84.73 % )
            Info: Total interconnect delay = 2.000 ns ( 15.27 % )
        Info: - Shortest clock path from clock "SW1" to source register is 8.500 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_33; Fanout = 12; CLK Node = 'SW1'
            Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'
                Info: Loc. = LC8; Node "fref~104"
            Info: 3: + IC(1.000 ns) + CELL(2.700 ns) = 8.500 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'
            Info: Total cell delay = 7.500 ns ( 88.24 % )
            Info: Total interconnect delay = 1.000 ns ( 11.76 % )
    Info: - Micro clock to output delay of source is 1.300 ns
    Info: - Shortest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'
        Info: 2: + IC(0.000 ns) + CELL(3.600 ns) = 3.600 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'
        Info: Total cell delay = 3.600 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.700 ns
Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock "SW2" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "wire_1" and destination pin or register "wire_1" for clock "SW2" (Hold time is 1.4 ns)
    Info: + Largest clock skew is 4.600 ns
        Info: + Longest clock path from clock "SW2" to destination register is 13.100 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_36; Fanout = 14; CLK Node = 'SW2'
            Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 3; COMB Node = 'fref~94'
            Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'
                Info: Loc. = LC8; Node "fref~104"
            Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'
            Info: Total cell delay = 11.100 ns ( 84.73 % )
            Info: Total interconnect delay = 2.000 ns ( 15.27 % )
        Info: - Shortest clock path from clock "SW2" to source register is 8.500 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_36; Fanout = 14; CLK Node = 'SW2'
            Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'
                Info: Loc. = LC8; Node "fref~104"
            Info: 3: + IC(1.000 ns) + CELL(2.700 ns) = 8.500 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'
            Info: Total cell delay = 7.500 ns ( 88.24 % )
            Info: Total interconnect delay = 1.000 ns ( 11.76 % )
    Info: - Micro clock to output delay of source is 1.300 ns
    Info: - Shortest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'
        Info: 2: + IC(0.000 ns) + CELL(3.600 ns) = 3.600 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'
        Info: Total cell delay = 3.600 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.700 ns
Info: tco from clock "f1hz" to destination pin "Counter_Clr" through register "wire_1" is 19.200 ns
    Info: + Longest clock path from clock "f1hz" to source register is 13.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_44; Fanout = 1; CLK Node = 'f1hz'
        Info: 2: + IC(0.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 3; COMB Node = 'fref~94'
        Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 4; COMB LOOP Node = 'fref~104'
            Info: Loc. = LC8; Node "fref~104"
        Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'
        Info: Total cell delay = 12.100 ns ( 92.37 % )
        Info: Total interconnect delay = 1.000 ns ( 7.63 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Longest register to pin delay is 4.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'wire_1'
        Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.600 ns; Loc. = LC7; Fanout = 1; COMB Node = 'Counter_Clr~4'
        Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 4.800 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'Counter_Clr'
        Info: Total cell delay = 3.800 ns ( 79.17 % )
        Info: Total interconnect delay = 1.000 ns ( 20.83 % )
Info: Longest tpd from source pin "SW1" to destination pin "dp_s100hz" is 5.000 ns
    Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_33; Fanout = 12; CLK Node = 'SW1'
    Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC5; Fanout = 2; COMB LOOP Node = 'dp_s100hz$latch~16'
        Info: Loc. = LC5; Node "dp_s100hz$latch~16"
    Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 5.000 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'dp_s100hz'
    Info: Total cell delay = 5.000 ns ( 100.00 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 12 warnings
    Info: Allocated 114 megabytes of memory during processing
    Info: Processing ended: Mon Jul 21 18:13:34 2008
    Info: Elapsed time: 00:00:04