counter.tan.qmsg

来自「频率计」· QMSG 代码 · 共 12 行 · 第 1/2 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "F_IN register lpm_counter:Q0_rtl_0\|dffs\[0\] register lpm_counter:Q0_rtl_0\|dffs\[0\] 140.85 MHz 7.1 ns Internal " "Info: Clock \"F_IN\" has Internal fmax of 140.85 MHz between source register \"lpm_counter:Q0_rtl_0\|dffs\[0\]\" and destination register \"lpm_counter:Q0_rtl_0\|dffs\[0\]\" (period= 7.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.800 ns + Longest register register " "Info: + Longest register to register delay is 4.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:Q0_rtl_0\|dffs\[0\] 1 REG LC67 45 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC67; Fanout = 45; REG Node = 'lpm_counter:Q0_rtl_0\|dffs\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(2.800 ns) 4.800 ns lpm_counter:Q0_rtl_0\|dffs\[0\] 2 REG LC67 45 " "Info: 2: + IC(2.000 ns) + CELL(2.800 ns) = 4.800 ns; Loc. = LC67; Fanout = 45; REG Node = 'lpm_counter:Q0_rtl_0\|dffs\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.800 ns" { lpm_counter:Q0_rtl_0|dffs[0] lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 58.33 % ) " "Info: Total cell delay = 2.800 ns ( 58.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 41.67 % ) " "Info: Total interconnect delay = 2.000 ns ( 41.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.800 ns" { lpm_counter:Q0_rtl_0|dffs[0] lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.800 ns" { lpm_counter:Q0_rtl_0|dffs[0] {} lpm_counter:Q0_rtl_0|dffs[0] {} } { 0.000ns 2.000ns } { 0.000ns 2.800ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F_IN destination 2.200 ns + Shortest register " "Info: + Shortest clock path from clock \"F_IN\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns F_IN 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'F_IN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { F_IN } "NODE_NAME" } } { "counter.v" "" { Text "R:/liu/counter/counter.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns lpm_counter:Q0_rtl_0\|dffs\[0\] 2 REG LC67 45 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC67; Fanout = 45; REG Node = 'lpm_counter:Q0_rtl_0\|dffs\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 100.00 % ) " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN {} F_IN~out {} lpm_counter:Q0_rtl_0|dffs[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F_IN source 2.200 ns - Longest register " "Info: - Longest clock path from clock \"F_IN\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns F_IN 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'F_IN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { F_IN } "NODE_NAME" } } { "counter.v" "" { Text "R:/liu/counter/counter.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns lpm_counter:Q0_rtl_0\|dffs\[0\] 2 REG LC67 45 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC67; Fanout = 45; REG Node = 'lpm_counter:Q0_rtl_0\|dffs\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 100.00 % ) " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN {} F_IN~out {} lpm_counter:Q0_rtl_0|dffs[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN {} F_IN~out {} lpm_counter:Q0_rtl_0|dffs[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN {} F_IN~out {} lpm_counter:Q0_rtl_0|dffs[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.800 ns" { lpm_counter:Q0_rtl_0|dffs[0] lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.800 ns" { lpm_counter:Q0_rtl_0|dffs[0] {} lpm_counter:Q0_rtl_0|dffs[0] {} } { 0.000ns 2.000ns } { 0.000ns 2.800ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN {} F_IN~out {} lpm_counter:Q0_rtl_0|dffs[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN {} F_IN~out {} lpm_counter:Q0_rtl_0|dffs[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_counter:Q0_rtl_0\|dffs\[0\] EN F_IN 3.800 ns register " "Info: tsu for register \"lpm_counter:Q0_rtl_0\|dffs\[0\]\" (data pin = \"EN\", clock pin = \"F_IN\") is 3.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.000 ns + Longest pin register " "Info: + Longest pin to register delay is 5.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns EN 1 PIN PIN_81 57 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_81; Fanout = 57; PIN Node = 'EN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "counter.v" "" { Text "R:/liu/counter/counter.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(2.800 ns) 5.000 ns lpm_counter:Q0_rtl_0\|dffs\[0\] 2 REG LC67 45 " "Info: 2: + IC(2.000 ns) + CELL(2.800 ns) = 5.000 ns; Loc. = LC67; Fanout = 45; REG Node = 'lpm_counter:Q0_rtl_0\|dffs\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.800 ns" { EN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 60.00 % ) " "Info: Total cell delay = 3.000 ns ( 60.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 40.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 40.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { EN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.000 ns" { EN {} EN~out {} lpm_counter:Q0_rtl_0|dffs[0] {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 0.200ns 2.800ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F_IN destination 2.200 ns - Shortest register " "Info: - Shortest clock path from clock \"F_IN\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns F_IN 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'F_IN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { F_IN } "NODE_NAME" } } { "counter.v" "" { Text "R:/liu/counter/counter.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns lpm_counter:Q0_rtl_0\|dffs\[0\] 2 REG LC67 45 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC67; Fanout = 45; REG Node = 'lpm_counter:Q0_rtl_0\|dffs\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 100.00 % ) " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN {} F_IN~out {} lpm_counter:Q0_rtl_0|dffs[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { EN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.000 ns" { EN {} EN~out {} lpm_counter:Q0_rtl_0|dffs[0] {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 0.200ns 2.800ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN {} F_IN~out {} lpm_counter:Q0_rtl_0|dffs[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "F_IN F_OUT F_OUT~reg0 3.900 ns register " "Info: tco from clock \"F_IN\" to destination pin \"F_OUT\" through register \"F_OUT~reg0\" is 3.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F_IN source 2.200 ns + Longest register " "Info: + Longest clock path from clock \"F_IN\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns F_IN 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'F_IN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { F_IN } "NODE_NAME" } } { "counter.v" "" { Text "R:/liu/counter/counter.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns F_OUT~reg0 2 REG LC16 1 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC16; Fanout = 1; REG Node = 'F_OUT~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { F_IN F_OUT~reg0 } "NODE_NAME" } } { "counter.v" "" { Text "R:/liu/counter/counter.v" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 100.00 % ) " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { F_IN F_OUT~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN {} F_IN~out {} F_OUT~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "counter.v" "" { Text "R:/liu/counter/counter.v" 14 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.400 ns + Longest register pin " "Info: + Longest register to pin delay is 0.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns F_OUT~reg0 1 REG LC16 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC16; Fanout = 1; REG Node = 'F_OUT~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { F_OUT~reg0 } "NODE_NAME" } } { "counter.v" "" { Text "R:/liu/counter/counter.v" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 0.400 ns F_OUT 2 PIN PIN_4 0 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 0.400 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'F_OUT'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { F_OUT~reg0 F_OUT } "NODE_NAME" } } { "counter.v" "" { Text "R:/liu/counter/counter.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.400 ns ( 100.00 % ) " "Info: Total cell delay = 0.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { F_OUT~reg0 F_OUT } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.400 ns" { F_OUT~reg0 {} F_OUT {} } { 0.000ns 0.000ns } { 0.000ns 0.400ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { F_IN F_OUT~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN {} F_IN~out {} F_OUT~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { F_OUT~reg0 F_OUT } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.400 ns" { F_OUT~reg0 {} F_OUT {} } { 0.000ns 0.000ns } { 0.000ns 0.400ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "lpm_counter:Q0_rtl_0\|dffs\[0\] EN F_IN -1.200 ns register " "Info: th for register \"lpm_counter:Q0_rtl_0\|dffs\[0\]\" (data pin = \"EN\", clock pin = \"F_IN\") is -1.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F_IN destination 2.200 ns + Longest register " "Info: + Longest clock path from clock \"F_IN\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns F_IN 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'F_IN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { F_IN } "NODE_NAME" } } { "counter.v" "" { Text "R:/liu/counter/counter.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns lpm_counter:Q0_rtl_0\|dffs\[0\] 2 REG LC67 45 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC67; Fanout = 45; REG Node = 'lpm_counter:Q0_rtl_0\|dffs\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 100.00 % ) " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN {} F_IN~out {} lpm_counter:Q0_rtl_0|dffs[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns EN 1 PIN PIN_81 57 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_81; Fanout = 57; PIN Node = 'EN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "counter.v" "" { Text "R:/liu/counter/counter.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(2.800 ns) 5.000 ns lpm_counter:Q0_rtl_0\|dffs\[0\] 2 REG LC67 45 " "Info: 2: + IC(2.000 ns) + CELL(2.800 ns) = 5.000 ns; Loc. = LC67; Fanout = 45; REG Node = 'lpm_counter:Q0_rtl_0\|dffs\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.800 ns" { EN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 60.00 % ) " "Info: Total cell delay = 3.000 ns ( 60.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 40.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 40.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { EN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.000 ns" { EN {} EN~out {} lpm_counter:Q0_rtl_0|dffs[0] {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 0.200ns 2.800ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN {} F_IN~out {} lpm_counter:Q0_rtl_0|dffs[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { EN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.000 ns" { EN {} EN~out {} lpm_counter:Q0_rtl_0|dffs[0] {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 0.200ns 2.800ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 21 15:41:50 2008 " "Info: Processing ended: Mon Jul 21 15:41:50 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}