counter10.v

来自「频率计」· Verilog 代码 · 共 25 行

module counter10(Clr,En,F_in,F_out,data_out);

output F_out;
output [3:0] data_out;
input Clr;
input En;
input F_in;

reg F_out;
reg [3:0] data_out;
always @(posedge F_in)
begin
	if((En == 1'b1)&&(Clr == 1'b0)&&(data_out != 4'b1001))
	begin
		data_out <= data_out + 4'b0001;
		F_out <= 1'b0;
	end
	else
	begin
		data_out <= 4'b0000;
		F_out <= 1'b1;
	end
end

endmodule