prev_cmp_main.tan.qmsg

来自「频率计」· QMSG 代码 · 共 22 行 · 第 1/5 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW1 register gate_control:inst3\|wire_1 register gate_control:inst3\|wire_2 33.56 MHz 29.8 ns Internal " "Info: Clock \"SW1\" has Internal fmax of 33.56 MHz between source register \"gate_control:inst3\|wire_1\" and destination register \"gate_control:inst3\|wire_2\" (period= 29.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns gate_control:inst3\|wire_1 1 REG LC237 115 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC237; Fanout = 115; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|wire_1 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.600 ns) 6.000 ns gate_control:inst3\|wire_2 2 REG LC238 24 " "Info: 2: + IC(3.400 ns) + CELL(2.600 ns) = 6.000 ns; Loc. = LC238; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns ( 43.33 % ) " "Info: Total cell delay = 2.600 ns ( 43.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.400 ns ( 56.67 % ) " "Info: Total interconnect delay = 3.400 ns ( 56.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { gate_control:inst3|wire_1 {} gate_control:inst3|wire_2 {} } { 0.000ns 3.400ns } { 0.000ns 2.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.700 ns - Smallest " "Info: - Smallest clock skew is -6.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 13.000 ns + Shortest register " "Info: + Shortest clock path from clock \"SW1\" to destination register is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW1 1 CLK PIN_193 12 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_193; Fanout = 12; CLK Node = 'SW1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW1 } "NODE_NAME" } } { "main.bdf" "" { Schematic "R:/liu/main/main.bdf" { { 248 -224 -56 264 "SW1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.800 ns) 7.100 ns gate_control:inst3\|fref~122 2 COMB LOOP LC225 4 " "Info: 2: + IC(0.000 ns) + CELL(6.800 ns) = 7.100 ns; Loc. = LC225; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~122'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~122 LC225 " "Info: Loc. = LC225; Node \"gate_control:inst3\|fref~122\"" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|fref~122 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|fref~122 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 19 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.800 ns" { SW1 gate_control:inst3|fref~122 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 13.000 ns gate_control:inst3\|wire_2 3 REG LC238 24 " "Info: 3: + IC(3.000 ns) + CELL(2.900 ns) = 13.000 ns; Loc. = LC238; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { gate_control:inst3|fref~122 gate_control:inst3|wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 76.92 % ) " "Info: Total cell delay = 10.000 ns ( 76.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 23.08 % ) " "Info: Total interconnect delay = 3.000 ns ( 23.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.000 ns" { SW1 gate_control:inst3|fref~122 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.000 ns" { SW1 {} SW1~out {} gate_control:inst3|fref~122 {} gate_control:inst3|wire_2 {} } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.800ns 2.900ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 source 19.700 ns - Longest register " "Info: - Longest clock path from clock \"SW1\" to source register is 19.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW1 1 CLK PIN_193 12 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_193; Fanout = 12; CLK Node = 'SW1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW1 } "NODE_NAME" } } { "main.bdf" "" { Schematic "R:/liu/main/main.bdf" { { 248 -224 -56 264 "SW1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(3.700 ns) 7.100 ns gate_control:inst3\|fref~112 2 COMB LC236 3 " "Info: 2: + IC(3.100 ns) + CELL(3.700 ns) = 7.100 ns; Loc. = LC236; Fanout = 3; COMB Node = 'gate_control:inst3\|fref~112'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.800 ns" { SW1 gate_control:inst3|fref~112 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 13.800 ns gate_control:inst3\|fref~122 3 COMB LOOP LC225 4 " "Info: 3: + IC(0.000 ns) + CELL(6.700 ns) = 13.800 ns; Loc. = LC225; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~122'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~122 LC225 " "Info: Loc. = LC225; Node \"gate_control:inst3\|fref~122\"" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|fref~122 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|fref~122 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 19 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.700 ns" { gate_control:inst3|fref~112 gate_control:inst3|fref~122 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 19.700 ns gate_control:inst3\|wire_1 4 REG LC237 115 " "Info: 4: + IC(3.000 ns) + CELL(2.900 ns) = 19.700 ns; Loc. = LC237; Fanout = 115; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { gate_control:inst3|fref~122 gate_control:inst3|wire_1 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.600 ns ( 69.04 % ) " "Info: Total cell delay = 13.600 ns ( 69.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.100 ns ( 30.96 % ) " "Info: Total interconnect delay = 6.100 ns ( 30.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "19.700 ns" { SW1 gate_control:inst3|fref~112 gate_control:inst3|fref~122 gate_control:inst3|wire_1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "19.700 ns" { SW1 {} SW1~out {} gate_control:inst3|fref~112 {} gate_control:inst3|fref~122 {} gate_control:inst3|wire_1 {} } { 0.000ns 0.000ns 3.100ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.700ns 6.700ns 2.900ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.000 ns" { SW1 gate_control:inst3|fref~122 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.000 ns" { SW1 {} SW1~out {} gate_control:inst3|fref~122 {} gate_control:inst3|wire_2 {} } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.800ns 2.900ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "19.700 ns" { SW1 gate_control:inst3|fref~112 gate_control:inst3|fref~122 gate_control:inst3|wire_1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "19.700 ns" { SW1 {} SW1~out {} gate_control:inst3|fref~112 {} gate_control:inst3|fref~122 {} gate_control:inst3|wire_1 {} } { 0.000ns 0.000ns 3.100ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.700ns 6.700ns 2.900ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.100 ns + " "Info: + Micro setup delay of destination is 1.100 ns" {  } { { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 55 -1 0 } } { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 21 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { gate_control:inst3|wire_1 {} gate_control:inst3|wire_2 {} } { 0.000ns 3.400ns } { 0.000ns 2.600ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.000 ns" { SW1 gate_control:inst3|fref~122 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.000 ns" { SW1 {} SW1~out {} gate_control:inst3|fref~122 {} gate_control:inst3|wire_2 {} } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.800ns 2.900ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "19.700 ns" { SW1 gate_control:inst3|fref~112 gate_control:inst3|fref~122 gate_control:inst3|wire_1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "19.700 ns" { SW1 {} SW1~out {} gate_control:inst3|fref~112 {} gate_control:inst3|fref~122 {} gate_control:inst3|wire_1 {} } { 0.000ns 0.000ns 3.100ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.700ns 6.700ns 2.900ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW0 register gate_control:inst3\|wire_1 register gate_control:inst3\|wire_2 41.32 MHz 24.2 ns Internal " "Info: Clock \"SW0\" has Internal fmax of 41.32 MHz between source register \"gate_control:inst3\|wire_1\" and destination register \"gate_control:inst3\|wire_2\" (period= 24.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns gate_control:inst3\|wire_1 1 REG LC237 115 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC237; Fanout = 115; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|wire_1 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.600 ns) 6.000 ns gate_control:inst3\|wire_2 2 REG LC238 24 " "Info: 2: + IC(3.400 ns) + CELL(2.600 ns) = 6.000 ns; Loc. = LC238; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns ( 43.33 % ) " "Info: Total cell delay = 2.600 ns ( 43.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.400 ns ( 56.67 % ) " "Info: Total interconnect delay = 3.400 ns ( 56.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { gate_control:inst3|wire_1 {} gate_control:inst3|wire_2 {} } { 0.000ns 3.400ns } { 0.000ns 2.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.900 ns - Smallest " "Info: - Smallest clock skew is -3.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW0 destination 13.000 ns + Shortest register " "Info: + Shortest clock path from clock \"SW0\" to destination register is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW0 1 CLK PIN_151 6 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_151; Fanout = 6; CLK Node = 'SW0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW0 } "NODE_NAME" } } { "main.bdf" "" { Schematic "R:/liu/main/main.bdf" { { 232 -224 -56 248 "SW0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.800 ns) 7.100 ns gate_control:inst3\|fref~122 2 COMB LOOP LC225 4 " "Info: 2: + IC(0.000 ns) + CELL(6.800 ns) = 7.100 ns; Loc. = LC225; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~122'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~122 LC225 " "Info: Loc. = LC225; Node \"gate_control:inst3\|fref~122\"" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|fref~122 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|fref~122 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 19 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.800 ns" { SW0 gate_control:inst3|fref~122 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 13.000 ns gate_control:inst3\|wire_2 3 REG LC238 24 " "Info: 3: + IC(3.000 ns) + CELL(2.900 ns) = 13.000 ns; Loc. = LC238; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { gate_control:inst3|fref~122 gate_control:inst3|wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 76.92 % ) " "Info: Total cell delay = 10.000 ns ( 76.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 23.08 % ) " "Info: Total interconnect delay = 3.000 ns ( 23.08 % )" {  } {  } 0 0 "Total inte