main.map.qmsg

来自「频率计」· QMSG 代码 · 共 51 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 21 11:44:32 2008 " "Info: Processing started: Mon Jul 21 11:44:32 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off main -c main " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off main -c main" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "main.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file main.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 main " "Info: Found entity 1: main" {  } { { "main.bdf" "" { Schematic "R:/liu/main/main.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "main " "Info: Elaborating entity \"main\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "main " "Warning: Processing legacy GDF or BDF entity \"main\" with Max+Plus II bus and instance naming rules" {  } { { "main.bdf" "" { Schematic "R:/liu/main/main.bdf" { } } }  } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "counter.v 1 1 " "Warning: Using design file counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.v" "" { Text "R:/liu/main/counter.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst\"" {  } { { "main.bdf" "inst" { Schematic "R:/liu/main/main.bdf" { { 0 136 256 160 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "gate_control.v 1 1 " "Warning: Using design file gate_control.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 gate_control " "Info: Found entity 1: gate_control" {  } { { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "gate_control gate_control:inst3 " "Info: Elaborating entity \"gate_control\" for hierarchy \"gate_control:inst3\"" {  } { { "main.bdf" "inst3" { Schematic "R:/liu/main/main.bdf" { { 208 80 224 368 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "fref gate_control.v(34) " "Warning (10240): Verilog HDL Always Construct warning at gate_control.v(34): inferring latch(es) for variable \"fref\", which holds its previous value in one or more paths through the always construct" {  } { { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 34 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "dp_s1hz gate_control.v(34) " "Warning (10240): Verilog HDL Always Construct warning at gate_control.v(34): inferring latch(es) for variable \"dp_s1hz\", which holds its previous value in one or more paths through the always construct" {  } { { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 34 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "dp_s10hz gate_control.v(34) " "Warning (10240): Verilog HDL Always Construct warning at gate_control.v(34): inferring latch(es) for variable \"dp_s10hz\", which holds its previous value in one or more paths through the always construct" {  } { { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 34 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "dp_s100hz gate_control.v(34) " "Warning (10240): Verilog HDL Always Construct warning at gate_control.v(34): inferring latch(es) for variable \"dp_s100hz\", which holds its previous value in one or more paths through the always construct" {  } { { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 34 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dp_s100hz gate_control.v(34) " "Info (10041): Inferred latch for \"dp_s100hz\" at gate_control.v(34)" {  } { { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 34 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dp_s10hz gate_control.v(34) " "Info (10041): Inferred latch for \"dp_s10hz\" at gate_control.v(34)" {  } { { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 34 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dp_s1hz gate_control.v(34) " "Info (10041): Inferred latch for \"dp_s1hz\" at gate_control.v(34)" {  } { { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 34 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "fref gate_control.v(34) " "Info (10041): Inferred latch for \"fref\" at gate_control.v(34)" {  } { { "gate_control.v" "" { Text "R:/liu/main/gate_control.v" 34 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fdiv.v(9) " "Warning (10268): Verilog HDL information at fdiv.v(9): Always Construct contains both blocking and non-blocking assignments" {  } { { "fdiv.v" "" { Text "R:/liu/main/fdiv.v" 9 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fdiv.v(24) " "Warning (10268): Verilog HDL information at fdiv.v(24): Always Construct contains both blocking and non-blocking assignments" {  } { { "fdiv.v" "" { Text "R:/liu/main/fdiv.v" 24 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fdiv.v(39) " "Warning (10268): Verilog HDL information at fdiv.v(39): Always Construct contains both blocking and non-blocking assignments" {  } { { "fdiv.v" "" { Text "R:/liu/main/fdiv.v" 39 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fdiv.v(54) " "Warning (10268): Verilog HDL information at fdiv.v(54): Always Construct contains both blocking and non-blocking assignments" {  } { { "fdiv.v" "" { Text "R:/liu/main/fdiv.v" 54 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "fdiv.v 1 1 " "Warning: Using design file fdiv.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 fdiv " "Info: Found entity 1: fdiv" {  } { { "fdiv.v" "" { Text "R:/liu/main/fdiv.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fdiv fdiv:inst1 " "Info: Elaborating entity \"fdiv\" for hierarchy \"fdiv:inst1\"" {  } { { "main.bdf" "inst1" { Schematic "R:/liu/main/main.bdf" { { 328 -48 48 456 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "dispdecoder.v 1 1 " "Warning: Using design file dispdecoder.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 dispdecoder " "Info: Found entity 1: dispdecoder" {  } { { "dispdecoder.v" "" { Text "R:/liu/main/dispdecoder.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dispdecoder dispdecoder:inst5 " "Info: Elaborating entity \"dispdecoder\" for hierarchy \"dispdecoder:inst5\"" {  } { { "main.bdf" "inst5" { Schematic "R:/liu/main/main.bdf" { { 224 496 696 480 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}