prev_cmp_fdiv.map.qmsg

频率计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 21 11:19:42 2008 " "Info: Processing started: Mon Jul 21 11:19:42 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fdiv -c fdiv " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fdiv -c fdiv" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fdiv.v(9) " "Warning (10268): Verilog HDL information at fdiv.v(9): Always Construct contains both blocking and non-blocking assignments" {  } { { "fdiv.v" "" { Text "R:/liu/fdiv/fdiv.v" 9 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fdiv.v(24) " "Warning (10268): Verilog HDL information at fdiv.v(24): Always Construct contains both blocking and non-blocking assignments" {  } { { "fdiv.v" "" { Text "R:/liu/fdiv/fdiv.v" 24 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fdiv.v(39) " "Warning (10268): Verilog HDL information at fdiv.v(39): Always Construct contains both blocking and non-blocking assignments" {  } { { "fdiv.v" "" { Text "R:/liu/fdiv/fdiv.v" 39 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fdiv.v(54) " "Warning (10268): Verilog HDL information at fdiv.v(54): Always Construct contains both blocking and non-blocking assignments" {  } { { "fdiv.v" "" { Text "R:/liu/fdiv/fdiv.v" 54 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fdiv.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fdiv.v" { { "Info" "ISGN_ENTITY_NAME" "1 fdiv " "Info: Found entity 1: fdiv" {  } { { "fdiv.v" "" { Text "R:/liu/fdiv/fdiv.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fdiv " "Info: Elaborating entity \"fdiv\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "4 " "Info: Inferred 4 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt4\[0\]~32 32 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: \"cnt4\[0\]~32\"" {  } { { "fdiv.v" "cnt4\[0\]~32" { Text "R:/liu/fdiv/fdiv.v" 54 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt3\[0\]~32 32 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: \"cnt3\[0\]~32\"" {  } { { "fdiv.v" "cnt3\[0\]~32" { Text "R:/liu/fdiv/fdiv.v" 39 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt2\[0\]~32 32 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: \"cnt2\[0\]~32\"" {  } { { "fdiv.v" "cnt2\[0\]~32" { Text "R:/liu/fdiv/fdiv.v" 24 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt1\[0\]~32 32 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: \"cnt1\[0\]~32\"" {  } { { "fdiv.v" "cnt1\[0\]~32" { Text "R:/liu/fdiv/fdiv.v" 9 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 248 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:cnt4_rtl_0 " "Info: Elaborated megafunction instantiation \"lpm_counter:cnt4_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "" 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "145 " "Info: Implemented 145 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_MCELLS" "140 " "Info: Implemented 140 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "R:/liu/fdiv/fdiv.map.smsg " "Info: Generated suppressed messages file R:/liu/fdiv/fdiv.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "143 " "Info: Allocated 143 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 21 11:19:48 2008 " "Info: Processing ended: Mon Jul 21 11:19:48 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}