fdiv.tan.qmsg

频率计

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "f10hz~reg0 " "Info: Detected ripple clock \"f10hz~reg0\" as buffer" {  } { { "fdiv.v" "" { Text "R:/liu/fdiv/fdiv.v" 39 0 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "f10hz~reg0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "f100hz~reg0 " "Info: Detected ripple clock \"f100hz~reg0\" as buffer" {  } { { "fdiv.v" "" { Text "R:/liu/fdiv/fdiv.v" 24 0 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "f100hz~reg0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "f1khz~reg0 " "Info: Detected ripple clock \"f1khz~reg0\" as buffer" {  } { { "fdiv.v" "" { Text "R:/liu/fdiv/fdiv.v" 9 0 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "f1khz~reg0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:cnt1_rtl_3\|dffs\[31\] register lpm_counter:cnt1_rtl_3\|dffs\[3\] 125.0 MHz 8.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 125.0 MHz between source register \"lpm_counter:cnt1_rtl_3\|dffs\[31\]\" and destination register \"lpm_counter:cnt1_rtl_3\|dffs\[3\]\" (period= 8.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.700 ns + Longest register register " "Info: + Longest register to register delay is 5.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cnt1_rtl_3\|dffs\[31\] 1 REG LC56 67 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC56; Fanout = 67; REG Node = 'lpm_counter:cnt1_rtl_3\|dffs\[31\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:cnt1_rtl_3|dffs[31] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(2.800 ns) 4.700 ns lpm_counter:cnt1_rtl_3\|dffs\[3\]~1101 2 COMB LC51 1 " "Info: 2: + IC(1.900 ns) + CELL(2.800 ns) = 4.700 ns; Loc. = LC51; Fanout = 1; COMB Node = 'lpm_counter:cnt1_rtl_3\|dffs\[3\]~1101'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { lpm_counter:cnt1_rtl_3|dffs[31] lpm_counter:cnt1_rtl_3|dffs[3]~1101 } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 5.700 ns lpm_counter:cnt1_rtl_3\|dffs\[3\] 3 REG LC52 41 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 5.700 ns; Loc. = LC52; Fanout = 41; REG Node = 'lpm_counter:cnt1_rtl_3\|dffs\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { lpm_counter:cnt1_rtl_3|dffs[3]~1101 lpm_counter:cnt1_rtl_3|dffs[3] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns ( 66.67 % ) " "Info: Total cell delay = 3.800 ns ( 66.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns ( 33.33 % ) " "Info: Total interconnect delay = 1.900 ns ( 33.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { lpm_counter:cnt1_rtl_3|dffs[31] lpm_counter:cnt1_rtl_3|dffs[3]~1101 lpm_counter:cnt1_rtl_3|dffs[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.700 ns" { lpm_counter:cnt1_rtl_3|dffs[31] {} lpm_counter:cnt1_rtl_3|dffs[3]~1101 {} lpm_counter:cnt1_rtl_3|dffs[3] {} } { 0.000ns 1.900ns 0.000ns } { 0.000ns 2.800ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.200 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fdiv.v" "" { Text "R:/liu/fdiv/fdiv.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns lpm_counter:cnt1_rtl_3\|dffs\[3\] 2 REG LC52 41 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC52; Fanout = 41; REG Node = 'lpm_counter:cnt1_rtl_3\|dffs\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { clk lpm_counter:cnt1_rtl_3|dffs[3] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 100.00 % ) " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { clk lpm_counter:cnt1_rtl_3|dffs[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { clk {} clk~out {} lpm_counter:cnt1_rtl_3|dffs[3] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.200 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fdiv.v" "" { Text "R:/liu/fdiv/fdiv.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns lpm_counter:cnt1_rtl_3\|dffs\[31\] 2 REG LC56 67 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC56; Fanout = 67; REG Node = 'lpm_counter:cnt1_rtl_3\|dffs\[31\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { clk lpm_counter:cnt1_rtl_3|dffs[31] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 100.00 % ) " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { clk lpm_counter:cnt1_rtl_3|dffs[31] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { clk {} clk~out {} lpm_counter:cnt1_rtl_3|dffs[31] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { clk lpm_counter:cnt1_rtl_3|dffs[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { clk {} clk~out {} lpm_counter:cnt1_rtl_3|dffs[3] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { clk lpm_counter:cnt1_rtl_3|dffs[31] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { clk {} clk~out {} lpm_counter:cnt1_rtl_3|dffs[31] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { lpm_counter:cnt1_rtl_3|dffs[31] lpm_counter:cnt1_rtl_3|dffs[3]~1101 lpm_counter:cnt1_rtl_3|dffs[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.700 ns" { lpm_counter:cnt1_rtl_3|dffs[31] {} lpm_counter:cnt1_rtl_3|dffs[3]~1101 {} lpm_counter:cnt1_rtl_3|dffs[3] {} } { 0.000ns 1.900ns 0.000ns } { 0.000ns 2.800ns 1.000ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { clk lpm_counter:cnt1_rtl_3|dffs[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { clk {} clk~out {} lpm_counter:cnt1_rtl_3|dffs[3] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { clk lpm_counter:cnt1_rtl_3|dffs[31] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { clk {} clk~out {} lpm_counter:cnt1_rtl_3|dffs[31] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk f1hz f1hz~reg0 21.900 ns register " "Info: tco from clock \"clk\" to destination pin \"f1hz\" through register \"f1hz~reg0\" is 21.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 20.200 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 20.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fdiv.v" "" { Text "R:/liu/fdiv/fdiv.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.700 ns) 3.500 ns f1khz~reg0 2 REG LC54 34 " "Info: 2: + IC(0.000 ns) + CELL(1.700 ns) = 3.500 ns; Loc. = LC54; Fanout = 34; REG Node = 'f1khz~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { clk f1khz~reg0 } "NODE_NAME" } } { "fdiv.v" "" { Text "R:/liu/fdiv/fdiv.v" 9 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(4.200 ns) 9.500 ns f100hz~reg0 3 REG LC16 34 " "Info: 3: + IC(1.800 ns) + CELL(4.200 ns) = 9.500 ns; Loc. = LC16; Fanout = 34; REG Node = 'f100hz~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { f1khz~reg0 f100hz~reg0 } "NODE_NAME" } } { "fdiv.v" "" { Text "R:/liu/fdiv/fdiv.v" 24 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(4.200 ns) 15.500 ns f10hz~reg0 4 REG LC19 34 " "Info: 4: + IC(1.800 ns) + CELL(4.200 ns) = 15.500 ns; Loc. = LC19; Fanout = 34; REG Node = 'f10hz~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { f100hz~reg0 f10hz~reg0 } "NODE_NAME" } } { "fdiv.v" "" { Text "R:/liu/fdiv/fdiv.v" 39 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(2.900 ns) 20.200 ns f1hz~reg0 5 REG LC38 1 " "Info: 5: + IC(1.800 ns) + CELL(2.900 ns) = 20.200 ns; Loc. = LC38; Fanout = 1; REG Node = 'f1hz~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { f10hz~reg0 f1hz~reg0 } "NODE_NAME" } } { "fdiv.v" "" { Text "R:/liu/fdiv/fdiv.v" 54 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.800 ns ( 73.27 % ) " "Info: Total cell delay = 14.800 ns ( 73.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.400 ns ( 26.73 % ) " "Info: Total interconnect delay = 5.400 ns ( 26.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "20.200 ns" { clk f1khz~reg0 f100hz~reg0 f10hz~reg0 f1hz~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "20.200 ns" { clk {} clk~out {} f1khz~reg0 {} f100hz~reg0 {} f10hz~reg0 {} f1hz~reg0 {} } { 0.000ns 0.000ns 0.000ns 1.800ns 1.800ns 1.800ns } { 0.000ns 1.800ns 1.700ns 4.200ns 4.200ns 2.900ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "fdiv.v" "" { Text "R:/liu/fdiv/fdiv.v" 54 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.400 ns + Longest register pin " "Info: + Longest register to pin delay is 0.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns f1hz~reg0 1 REG LC38 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC38; Fanout = 1; REG Node = 'f1hz~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { f1hz~reg0 } "NODE_NAME" } } { "fdiv.v" "" { Text "R:/liu/fdiv/fdiv.v" 54 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 0.400 ns f1hz 2 PIN PIN_24 0 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 0.400 ns; Loc. = PIN_24; Fanout = 0; PIN Node = 'f1hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { f1hz~reg0 f1hz } "NODE_NAME" } } { "fdiv.v" "" { Text "R:/liu/fdiv/fdiv.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.400 ns ( 100.00 % ) " "Info: Total cell delay = 0.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { f1hz~reg0 f1hz } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.400 ns" { f1hz~reg0 {} f1hz {} } { 0.000ns 0.000ns } { 0.000ns 0.400ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "20.200 ns" { clk f1khz~reg0 f100hz~reg0 f10hz~reg0 f1hz~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "20.200 ns" { clk {} clk~out {} f1khz~reg0 {} f100hz~reg0 {} f10hz~reg0 {} f1hz~reg0 {} } { 0.000ns 0.000ns 0.000ns 1.800ns 1.800ns 1.800ns } { 0.000ns 1.800ns 1.700ns 4.200ns 4.200ns 2.900ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { f1hz~reg0 f1hz } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.400 ns" { f1hz~reg0 {} f1hz {} } { 0.000ns 0.000ns } { 0.000ns 0.400ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "116 " "Info: Allocated 116 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 21 19:42:56 2008 " "Info: Processing ended: Mon Jul 21 19:42:56 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}