top.v

rs232控制器

//-----------------------------------------------------------------------------
//
// Author: John Clayton
// Date  : Aug.   20, 2002
// Update: Jan.   10, 2003 Obtained this file from "build_14" project.
//
// Description
//-----------------------------------------------------------------------------
// This targets an XC2S200E board which was created for educational purposes.
//
// There are:
//    8  LEDs (led[7:0])
//    4  switches (switch[3:0])
//    1  clock, present on GCLK1
//    1  clock, present on GCLK0
//    Many different I/O lines.  See PNDKR-1E reference manual for more details
//-----------------------------------------------------------------------------
//
// NOTE: This build is for testing out read only regs inside of reg_8_pack
//
// The following 'include line must be used with Synplify to create EDIF
// The line must be commented for ModelSim.
//`include "d:\synplicity\synplify_70\lib\xilinx\virtex.v"

// The following directive is for Xilinx XST 5.1 synthesis, and it is
// required in order to prevent the optimization phase from removing some
// blocks which are critical to the operation of the design.  In essence, the
// synthesizer views these blocks as having all outputs unconnected, and so
// it decides that they couldn't possibly affect any other logic, and therefore
// they should be trimmed.  Unfortunately, the XST tool seems to only check
// ports of type "output" and it neglects ports of type "inout" so that the
// "read_8_pack" gets trimmed away, and also the "reg_8_pack" without any
// connected register outputs gets trimmed.

////synthesis attribute s of dat is yes;

`define CLK_DDS_BIT_WIDTH 9

module top (
  clk_0,
  switch,
  led,
  extra,           // extra pads
  A,
  rs232_0_o,       // rs232 is B port
  rs232_0_i,
  rs232_1_o,
  rs232_1_i,
  C,
  D,
  E,
  F,
  );

// I/O declarations
input clk_0;      // 48 MHz
input [3:0] switch;
input rs232_0_i;
input rs232_1_i;

output [12:0] extra;
output [7:0] led;
output [7:0] A;
output [15:0] C;
output [47:0] D;
output [17:0] E;
output [17:0] F;
output rs232_0_o;
output rs232_1_o;

// Internal signal declarations

wire [4:0] r0_wire;  // "Read" regs.  Used to "hold" pin locations, so that
                     // the synthesis tools do not complain about these pins
                     // being present in the constraints file and not in the
                     // design...

     // System Clock signals
wire var_clk_unbuffered;
wire var_clk;
reg  var_clk_half_unbuffered;
wire var_clk_half;
wire clk_1x_dll;
wire clk_2x;
wire clk_2x_dll;
wire clk_halfx_dll;
wire lcd_clk;
wire [`CLK_DDS_BIT_WIDTH-1:0] sys_clk_freq;

    // Processor interrupt signals
wire slow_int;                 // For checking long interrupt requests
wire periodic_int;             // For checking short interrupt requests
wire periodic_int_enable;      // Enables periodic interrupt
reg  [21:0] int_counter;

     // Signals from risc processor
wire [15:0] risc_aux_adr;     // AUX (expansion) bus
wire        risc_aux_we;      // AUX we
wire [15:0] risc_prog_dat;    // Program data
wire [12:0] risc_prog_adr;    // (Up to 8k words possible)
wire [8:0]  risc_ram_adr;     // RAM file address
wire [7:0]  risc_ram_dat_o;   // RAM file data
wire [7:0]  risc_ram_dat_i;   // RAM file data
wire        risc_ram_we;      // RAM we
wire        risc_stb;         // Clock enable for risc processor

     // Signals from rs232_syscon
wire [15:0] adr;        // A side address
wire [7:0] dat;         // A side data
wire we;
wire stb;
wire rst;
wire master_br;

    // Address decode signals
wire       code_space;  // High for access to code space (AUX bus)
wire       rgb_space;   // High for access to rgb space (AUX bus)
wire       io_space;    // High for access to I/O space (AUX bus)
wire [3:0] io_sel;      // 1 of these is active high for I/O space accesses
wire sel_0;
wire sel_1;
wire sel_2;

    // Hardware breakpoint and single stepping signals
wire [12:0] break_prog_adr;  // For hardware breakpoint on prog. adr
wire [13:0] break_prog_dat;  // For hardware breakpoint on prog. dat
wire [ 1:0] break_enable;    // bit 1: enables dat BP, bit 0: enables adr BP
wire        breakpoint;      // 1 = any breakpoint condition encountered.
reg  [ 5:0] step_count;      // Number of steps remaining to execute
wire [ 5:0] clocks_to_step;  // Desired number of steps to execute
wire        begin_stepping;       // Automatically resets itself when written!
wire        stepping_active;      // 1 during single stepping
wire        reset_single_stepper; // 1 during breakpoint or reset
wire [ 3:0] processor_control; // For manipulating the processor
wire        run_free;          // Allows processor to run constantly
wire        forced_reset;      // Forces the processor into reset
wire        bus_rdy;           // 1 = processor can execute this clock cycle.

    // A side RAM signals
wire [7:0] code_ram_dat_o;
wire [2:0] rgb_ram_dat_o;
wire [7:0] regfile_ram_dat_o;

    // B side (Peripheral side) RAM signals
wire [2:0]  pixel_dat;
wire [13:0] pixel_adr;   // (12288 pixels addressed)

    // Other...
wire reset = switch[0];  // Simply a renaming exercise

wire [7:0] led_r7;

//--------------------------------------------------------------------------
// Clock generation
//--------------------------------------------------------------------------


// This Xilinx DLL provides clock doubling.
// It also provides delay compensation, duty cycle correction and it can
// divide by 1.5, 2, 2.5, 3, 4, 5, 8 or 16.  The divided clock output
// also will have 50% duty cycle, regardless of the division factor.
// The CLKDV_DIVIDE property determines the division factor (default = 2).

//CLKDLL dll2x (
//              .CLKIN(clk_0),
//              .CLKFB(clk_2x),
//              .RST(reset),
//              .CLK0(clk_1x_dll),
//              .CLK90(),
//              .CLK180(),
//              .CLK270(),
//              .CLK2X(clk_2x_dll),
//              .CLKDV(clk_halfx_dll),
//              .LOCKED(locked2x)
//              );

//BUFG  clk2xg (
//              .I(clk_2x_dll),
//              .O(clk_2x)
//              );

assign lcd_clk = var_clk_half;

//// This block generates a variable frequency system clock
//assign sys_clk_freq = `CLK_DDS_BIT_WIDTH'h080;
//square_wave_dds #(
//                  `CLK_DDS_BIT_WIDTH       // DDS counter length
//                  )
//dds1
//   (
//    .clk(clk_2x),
//    .clk_en(1'b1),
//    .reset(reset),
//    .frequency(sys_clk_freq),
//    .clk_o(var_clk_unbuffered)
//    );

// This generates a half speed clock from the full speed variable clock
always @(posedge var_clk)
begin
  var_clk_half_unbuffered <= ~var_clk_half_unbuffered;
end

// BUFG provides very low skew clocks to the entire array of logic.

BUFG  clkbuf0 (
               .I(clk_0),
               .O(var_clk)
               );

BUFG  clkbuf1 (
               .I(var_clk_half_unbuffered),
               .O(var_clk_half)
               );


//--------------------------------------------------------------------------
// Instantiations
//--------------------------------------------------------------------------

// Assign values to unused ports
assign rs232_1_o = rs232_1_i;
assign extra = 13'hzzzz;
assign A = 8'hzz;
assign D = 48'hzzzzzzzzzzzz;
assign E = 18'hzzzzz;
assign F = 18'hzzzzz;

// This is for monitoring signals using a logic analyzer

// This block runs the flat panel display (5x5 pixels)
vga_128_by_92 lcd_block (
  .lcd_clk(lcd_clk),
  .lcd_reset(reset),
  .pixel_dat_i(pixel_dat),
  .pixel_adr_o(pixel_adr),
  .lcd_drive(C)
  );

// This block is the risc microcontroller
assign risc_stb = (bus_rdy || rst);
risc16f84_clk2x 
  processor1
  (
   .prog_dat_i(risc_prog_dat[13:0]),  // [13:0] ROM read data
   .prog_adr_o(risc_prog_adr),        // [12:0] ROM address
   .ram_dat_i(risc_ram_dat_i),        // [7:0] RAM read data
   .ram_dat_o(risc_ram_dat_o),        // [7:0] RAM write data
   .ram_adr_o(risc_ram_adr),          // [8:0] RAM address
   .ram_we_o(risc_ram_we),            // RAM write strobe (H active)
   .aux_adr_o(risc_aux_adr),          // [15:0] Auxiliary address bus
   .aux_dat_io(dat),                  // [7:0] AUX data (shared w/rs232_syscon)
   .aux_we_o(risc_aux_we),            // Auxiliary write strobe (H active)
   .int0_i(periodic_int || slow_int), // PORT-B(0) INT
   .reset_i(rst || forced_reset),     // Power-on reset (H active)
   .clk_en_i(risc_stb),               // Clock enable for all clocked logic
   .clk_i(var_clk_half)               // Clock input
   );