mouse1.v

PS2鼠标驱动程序

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    01:35:51 07/31/2007 
// Design Name: 
// Module Name:    mouse1 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module mouse_ctrl(clk, reset, KD, KC, an, sseg, led, Lclick, Mclick, Rclick, Xmv, Ymv, Xmvrate, Ymvrate);
    
	 input clk;
    	 input reset;
   	 inout KD;
   	 inout KC;
    	output [3:0] an;
   	 output [7:0] sseg;
	 output [7:0] led;
	 output Lclick;
	 output Rclick;
	 output Mclick;
	 output Xmv;
	 output Ymv;
	 output [7:0] Xmvrate;
	 output [7:0] Ymvrate;
	 reg [3:0] an;
	 reg [7:0] sseg;
	 reg [25:0] clkDiv;
	 reg KDI,KCI;
	 reg [32:0] sr;//?
	 reg [15:0] wr;//?
	 reg [1:0] init;
	 wire sclk,pclk;
	 wire [3:0] out,tmp1,tmp2;
	 reg [5:0] x;
	 reg [1:0] anctr;
	 reg [7:0] led;
	 reg [3:0] counter;
	 reg Lclick,Rclick,Mclick,Xmv,Ymv;
	 reg [7:0] Xmvrate,Ymvrate;
	 reg [5:0] stable;	 
	 
	 	
assign sclk=clkDiv[15];
assign pclk=clkDiv[3];
assign out=(anctr==0)?wr[7:4]:tmp1[3:0];
assign tmp1=(anctr==1)?wr[3:0]:tmp2[3:0];
assign tmp2=(anctr==2)?wr[15:12]:wr[11:8];
assign KC=(init==2'b11)?1'bz:1'b0;
assign KD=(counter==0)?1'b0:
	   (counter==1)?1'b0:
	   (counter==2)?1'b0:
	   (counter==3)?1'b1:
	   (counter==4)?1'b0:
	   (counter==5)?1'b1:
	   (counter==6)?1'b1:
	   (counter==7)?1'b1:
	   (counter==8)?1'b1:
	   (counter==9)?1'b0:
	   (counter==10)?1'b1:1'bz;

always@(posedge sclk or posedge reset)
begin
	if(reset==1)
	begin
		anctr<=0;
		an<=4'b1111;
		init<=0;
	end
	else
	begin
		anctr<=anctr+1;
		if(init==2'b11) init<=2'b11;
		else init<=init+1;
		case(anctr)
			0:an<=4'b0111;
			1:an<=4'b1110;
			2:an<=4'b1101;
			3:an<=4'b1011;
		endcase
	end
end

always@(posedge clk or posedge reset)
begin
	if(reset==1) clkDiv<=0;
	else clkDiv<=clkDiv+1;
end

always@(posedge pclk or posedge reset)
begin
	if(reset==1)
	begin
		KDI<=0;
		KCI<=0;
	end
	else
	begin
		KDI<=KD;
		KCI<=KC;
	end
end

always@(negedge KCI or posedge reset)
begin
	if(reset==1)
	begin
		sr<=0;
		x<=0;
		counter<=0;
	end
	else
	begin
		if(counter==11) 
		begin
			if(x==32) x<=0;
			else x<=x+1;
		end
		else counter<=counter+1;
		sr<={sr[33:0],KDI};
	end
end

always@(posedge sclk or posedge reset)
begin
	if(reset==1) stable<=0;
	else
	begin
		if(KCI==1)
		begin
			if(stable==63) stable<=63;
			else stable<=stable+1;
		end
		else stable<=0;
	end
end

always@(x or stable)
begin
	if(x==32&&stable!=63)
	begin
		Ymvrate <= sr[8:1];
		Xmvrate <= sr[30:23];
		Ymv <= sr[17];
		Xmv <= sr[16];
		Mclick<=sr[14];
		Rclick<=sr[13];
		Lclick<=sr[12];
		wr[15:8] <= sr[30:23];
		wr[7:0] <= sr[8:1];
		led<=sr[19:12];
	end
	else if (stable==63)
	begin
		Ymvrate <= 0;
		Xmvrate <= 0;
		Ymv <= 0;
		Xmv <= 0;
		Mclick <= 0;
		Rclick <= 0;
		Lclick <= 0;
		wr[15:8] <= 0;
		wr[7:0] <= 0;
		led <= 0;
	end
end

always@(out)
begin
	case(out)
		4'b0000:sseg<=8'b11000000;
		4'b0001:sseg<=8'b11111001;
		4'b0010:sseg<=8'b10100100;
		4'b0011:sseg<=8'b10110000;
		4'b0100:sseg<=8'b10011001;
		4'b0101:sseg<=8'b10010010;
		4'b0110:sseg<=8'b10000010;
		4'b0111:sseg<=8'b11111000;
		4'b1000:sseg<=8'b10000000;
		4'b1001:sseg<=8'b10010000;
		4'b1010:sseg<=8'b10001000;
		4'b1011:sseg<=8'b10000011;
		4'b1100:sseg<=8'b11000110;
		4'b1101:sseg<=8'b10100001;
		4'b1110:sseg<=8'b10000110;
		4'b1111:sseg<=8'b10001110;
		default:sseg<=8'b11111111;
	endcase
end
endmodule