cpu.h

Keil C 51单片机串口通信程序, 通过该程序可以了解和使用单片机串口通信

sbit TL2_5  = TL2^5;
sbit TL2_4  = TL2^4;
sbit TL2_3  = TL2^3;
sbit TL2_2  = TL2^2;
sbit TL2_1  = TL2^1;
sbit TL2_0  = TL2^0;
*/

/*
// TH2: TIMER 2 MSB, TH2.7 TH2.6 TH2.5 TH2.4 TH2.3 TH2.2 TH2.1 TH2.0
sbit TH2_7  = TH2^7;
sbit TH2_6  = TH2^6;
sbit TH2_5  = TH2^5;
sbit TH2_4  = TH2^4;
sbit TH2_3  = TH2^3;
sbit TH2_2  = TH2^2;
sbit TH2_1  = TH2^1;
sbit TH2_0  = TH2^0;
*/

///////////////////////
// WinBond extension //
///////////////////////

/*
// DPL1: DATA POINTER LOW1, DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0
sbit DPL1_7 = DPL1^7;
sbit DPL1_6 = DPL1^6;
sbit DPL1_5 = DPL1^5;
sbit DPL1_4 = DPL1^4;
sbit DPL1_3 = DPL1^3;
sbit DPL1_2 = DPL1^2;
sbit DPL1_1 = DPL1^1;
sbit DPL1_0 = DPL1^0;
*/

/*
// DPH1: DATA POINTER HIGH1, DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0
sbit DPH1_7 = DPH1^7;
sbit DPH1_6 = DPH1^6;
sbit DPH1_5 = DPH1^5;
sbit DPH1_4 = DPH1^4;
sbit DPH1_3 = DPH1^3;
sbit DPH1_2 = DPH1^2;
sbit DPH1_1 = DPH1^1;
sbit DPH1_0 = DPH1^0;
*/

/*
// DPS: DATA POINTER SELECT, - - - - - - - DPS.0
sbit DPS_0 = DPS^0; // This bit is used to select either the DPL,DPH pair or the DPL1,DPH1 pair as the active Data Pointer. When set to 1, DPL1, DPH1 will be selected, otherwise DPL,DPH will be selected.
*/

/*
// CKCON: CLOCK CONTROL, WD1 WD0 T2M T1M T0M MD2 MD1 MD0
sbit WD1  = CKCON^7; // WD1-0:Watchdog timer mode select bits: These bits determine the time-out period for the watchdog timer. In all four time-out options the reset time-out is 512 clocks more than the interrupt timeout period.
sbit WD0  = CKCON^6; // 	WD1 WD0  Interrupt time-out  Reset time-out
					 //		 0   0          2^17           2^17 + 512
					 //		 0   1          2^20           2^20 + 512
					 //      1   0          2^23           2^23 + 512
					 //      1   1          2^26           2^26 + 512
sbit T2M  = CKCON^5; // Timer 2 clock select: When T2M is set to 1, timer 2 uses a divide by 4 clock, and when set to 0 it uses a divide by 12 clock.
sbit T1M  = CKCON^4; // Timer 1 clock select: When T1M is set to 1, timer 1 uses a divide by 4 clock, and when set to 0 it uses a divide by 12 clock.
sbit T0M  = CKCON^3; // Timer 0 clock select: When T0M is set to 1, timer 0 uses a divide by 4 clock, and when set to 0 it uses a divide by 12 clock.
sbit MD2  = CKCON^2; // MD2-0: Stretch MOVX select bits: These three bits are used to select the stretch value for the MOVX instruction. Using a variable MOVX length enables the user to access slower external memory devices or peripherals without the need for external circuits. The RD or WR strobe will be stretched by the selected interval. When accessing the on-chip SRAM, the MOVX instruction is always in 2 machine cycles regardless of the stretch setting. By default, the stretch has value of 1. If the user needs faster accessing, then a stretch value of 0 should be selected.
sbit MD1  = CKCON^1; // 	MD2 MD1 MD0  Stretch value   MOVX duration
sbit MD0  = CKCON^0; //      0   0   0          0        2 machine cycles
					 //      0   0   1          1        3 machine cycles (Default)
					 //      0   1   0          2 		 4 machine cycles
					 //      0   1   1 			3 		 5 machine cycles
					 //      1   0   0 			4 		 6 machine cycles
					 //      1   0   1 			5 		 7 machine cycles
					 //      1   1   0 			6 		 8 machine cycles
					 //      1   1   1 			7 		 9 machine cycles
*/

/*
// EXIF: EXTERNAL INTERRUPT FLAG, IE5 IE4 IE3 IE2 XT/RG RGMD RGSL -
sbit IE5   = EXIF^7; // External Interrupt 5 flag. Set by hardware when a falling edge is detected on INT5 .
sbit IE4   = EXIF^6; // External Interrupt 4 flag. Set by hardware when a rising edge is detected on INT4.
sbit IE3   = EXIF^5; // External Interrupt 3 flag. Set by hardware when a falling edge is detected on INT3 .
sbit IE2   = EXIF^4; // External Interrupt 2 flag. Set by hardware when a rising edge is detected on INT2.
sbit XT_RG = EXIF^3; // Crystal/RC Oscillator Select. Setting this bit selects crystal or external clock as system clock source. Clearing this bit selects the on-chip RC oscillator as clock source. XTUP(STATUS.4) must be set to 1 and XTOFF (PMR.3) must be cleared before this bit can be set. Attempts to set this bit without obeying these conditions will be ignored. This bit is set to 1 after a poweron reset and unchanged by other forms of reset.
sbit RGMD  = EXIF^2; // RC Mode Status. This bit indicates the current clock source of microcontroller. When cleared, CPU is operating from the external crystal or oscillator. When set, CPU is operating from the on-chip RC oscillator. This bit is cleared to 0 after a power-on reset and unchanged by other forms of reset.
sbit RGSL  = EXIF^1; // RC Oscillator Select. This bit selects the clock source following a resume from Power Down Mode. Setting this bit allows device operating from RC oscillator when a resume from Power Down Mode. When this bit is cleared, the device will hold operation until the crystal oscillator has warmed-up following a resume from Power Down Mode. This bit is cleared to 0 after a power-on reset and unchanged by other forms of reset.
*/

/*
// P4: PORT 4, - - - - P4.3 P4.2 P4.1 P4.0
sbit P4_3  = P4^3;
sbit P4_2  = P4^2;
sbit P4_1  = P4^1;
sbit P4_0  = P4^0;
*/

// SCON1: SERIAL PORT CONTROL 1, SM0_1/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1
sbit SM0_1_FE_1 = SCON1^7; // Serial port 1, Mode 0 bit or Framing Error Flag 1: The SMOD0 bit in PCON SFR determines whether this bit acts as SM0_1 or as FE_1. the operation of SM0_1 is described below. When used as FE_1, this bit will be set to indicate an invalid stop bit. This bit must be manually cleared in software to clear the FE_1 condition.
sbit SM1_1  	= SCON1^6; // Serial port 1 Mode bit 1:
						   // 	SM0_1 SM1_1  Mode Description  Length  Baudrate
						   //     0     0    0 Synchronous        8    4/12 Tclk
						   // 	  0     1    1 Asynchronous      10    variable
						   //     1     0    2 Asynchronous      11    64/32 Tclk
						   // 	  1     1    3 Asynchronous      11    variable
sbit SM2_1  	= SCON1^5; // Multiple processors communication. Setting this bit to 1 enables the multiprocessor communication feature in mode 2 and 3. In mode 2 or 3, if SM2_1 is set to 1, then RI_1 will not be activated if the received 9th data bit (RB8_1) is 0. In mode 1, if SM2_1 = 1, then RI_1 will not be activated if a valid stop bit was not received. In mode 0, the SM2_1 bit controls the serial port 1 clock. If set to 0, then the serial port 1 runs at a divide by 12 clock of the oscillator. This gives compatibility with the standard 8052. When set to 1, the serial clock become divide by 4 of the oscillator clock. This results in faster synchronous serial communication.
sbit REN_1  	= SCON1^4; // Receive enable: When set to 1 serial reception is enabled, otherwise reception is disabled.
sbit TB8_1  	= SCON1^3; // This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared by software as desired.
sbit RB8_1  	= SCON1^2; // In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2_1 = 0, RB8_1 is the stop bit that was received. In mode 0 it has no function.
sbit TI_1  		= SCON1^1; // Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in all other modes during serial transmission. This bit must be cleared by software.
sbit RI_1 		= SCON1^0; // Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bits time in the other modes during serial reception. However the restrictions of SM2_1 apply to this bit. This bit can be cleared only by software.

/*
// SBUF1: SERIAL DATA BUFFER 1, SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0
sbit SBUF1_7 = SBUF1^7;
sbit SBUF1_6 = SBUF1^6;
sbit SBUF1_5 = SBUF1^5;
sbit SBUF1_4 = SBUF1^4;
sbit SBUF1_3 = SBUF1^3;
sbit SBUF1_2 = SBUF1^2;
sbit SBUF1_1 = SBUF1^1;
sbit SBUF1_0 = SBUF1^0;
*/

/*
// ROMMAP: ROMMAP, WS 1 - - - - - -
sbit WS    = ROMMAP^7;
*/

/*
// PMR: POWER MANAGEMENT REGISTER, CD1 CD0 SWB - XTOFF ALE-OFF - DME0
sbit CD1     = PMR^7; // CD1,CD0: Clock Divide Control. These bit selects the number of clocks required to generate one machine cycle. There are three modes including divide by 4, 64 or 1024. Switching between modes must first go back devide by 4 mode. For instance, to go from 64 to 1024 clocks/machine cycle the device must first go from 64 to 4 clocks/machine cycle, and then from 4 to 1024 clocks/machine cycle.
sbit CD0     = PMR^6; // 	CD1, CD0  clocks/machine cycle
					  //     0    0   Reserved
					  //     0 	  1 	  4
					  //     1 	  0  	 64
					  //     1 	  1    1024
sbit SWB     = PMR^5; // Switchback Enable. Setting this bit allows an enabled external interrupt or serial port activity to force the CD1,CD0 to divide by 4 state (0,1). The device will switch modes at the start of the jump to interrupt service routine while a external interrupt is enabled and actually recongnized by microcontroller. While a serial port reception, the switchback occurs at the start of the instruction following the falling edge of the start bit.
sbit XTOFF   = PMR^3; // Crystal Oscillator Disable. Setting this bit disables the external crystal oscillator. This bit can only be set to 1 while the microcontroller is operating from the RC oscillator. Clearing this bit restarts the crystal oscillator, the XTUP (STATUS.4) bit will be set after crystal oscillator warmed-up has completed.
sbit ALE_OFF = PMR^2; // This bit disables the expression of the ALE signal on the device pin during all on-board program and data memory accesses. External memory accesses will automatically enable ALE independent of ALEOFF. 0 = ALE expression is enable; 1 = ALE expression is disable
sbit DME0    = PMR^0; // This bit determines the on-chip MOVX SRAM to be enabled or disabled. Set this bit to 1 will enable the on-chip 1KB MOVX SRAM.
*/

/*
// STATUS: STATUS REGISTER, - HIP LIP XTUP SPTA1 SPRA1 SPTA0 SPRA0
sbit HIP   = STATUS^6; // High Priority Interrupt Status. When set, it indicates that software is servicing a high priority interrupt. This bit will be cleared when the program executes the corresponding RETI instruction.
sbit LIP   = STATUS^5; // Low Priority Interrupt Status. When set, it indicates that software is servicing a low priority interrupt. This bit will be cleared when the program executes the corresponding RETI instruction.
sbit XTUP  = STATUS^4; // Crystal Oscillator Warm-up Status. when set, this bit indicates CPU has detected clock to be ready. Each time the crystal oscillator is restarted by exit from power down mode or the XTOFF bit is set, hardware will clear this bit. This bit is set to 1 after a power-on reset. When this bit is cleared, it prevents software from setting the XT/RG bit to enable CPU operation from crystal oscillator.
sbit SPTA1 = STATUS^3; // Serial Port 1 Transmit Activity. This bit is set during serial port 1 is currently transmitting data. It is cleared when TI_1 bit is set by hardware. Changing the Clock Divide Control bits CD0,CD1 will be ignored when this bit is set to 1 and SWB = 1.
sbit SPRA1 = STATUS^2; // Serial Port 1 Receive Activity. This bit is set during serial port 1 is currently receiving a data. It is cleared when RI_1 bit is set by hardware. Changing the Clock Divide Control bits CD0,CD1 will be ignored when this bit is set to 1 and SWB = 1.
sbit SPTA0 = STATUS^1; // Serial Port 0 Transmit Activity. This bit is set during serial port 0 is currently transmitting data. It is cleared when TI bit is set by hardware. Changing the Clock Divide Control bits CD0,CD1 will be ignored when this bit is set to 1 and SWB = 1.
sbit SPRA0 = STATUS^0; // Serial Port 0 Receive Activity. This bit is set during serial port 0 is currently receiving a data. It is cleared when RI bit is set by hardware. Changing the Clock Divide Control bits CD0,CD1 will be ignored when this bit is set to 1 and SWB = 1.
*/

/*
// TA: TIMED ACCESS, TA.7 TA.6 TA.5 TA.4 TA.3 TA.2 TA.1 TA.0
sbit TA_7  = TA^7;
sbit TA_6  = TA^6;
sbit TA_5  = TA^5;
sbit TA_4  = TA^4;
sbit TA_3  = TA^3;
sbit TA_2  = TA^2;
sbit TA_1  = TA^1;
sbit TA_0  = TA^0;
*/

// WDCON: WATCHDOG CONTROL, SMOD_1 POR - - WDIF WTRF EWT RWT
sbit SMOD_1 = WDCON^7; // This bit doubles the Serial Port 1 baud rate in mode 1, 2, and 3 when set to 1.
sbit POR    = WDCON^6; // Power-on reset flag. Hardware will set this flag on a power up condition. This flag can be read or written by software. A write by software is the only way to clear this bit once it is set.
sbit WDIF   = WDCON^3; // Watchdog Timer Interrupt Flag. If the watchdog interrupt is enabled, hardware will set this bit to indicate that the watchdog interrupt has occurred. If the interrupt is not enabled, then this bit indicates that the time-out period has elapsed. This bit must be cleared by software.
sbit WTRF   = WDCON^2; // Watchdog Timer Reset Flag. Hardware will set this bit when the watchdog timer causes a reset. Software can read it but must clear it manually. A power-fail reset will also clear the bit. This bit helps software in determining the cause of a reset. If EWT = 0, the watchdog timer will have no affect on this bit.
sbit EWT    = WDCON^1; // Enable Watchdog timer Reset. Setting this bit will enable the Watchdog timer Reset function.
sbit RWT    = WDCON^0; // Reset Watchdog Timer. This bit helps in putting the watchdog timer into a know state. It also helps in resetting the watchdog timer before a time-out occurs. Failing to set the EWT before time-out will cause an interrupt, if EWDI (EIE.4) is set, and 512 clocks after that a watchdog timer reset will be generated if EWT is set. This bit is self-clearing by hardware.

// EIE: EXTENDED INTERRUPT ENABLE, - - - EWDI EX5 EX4 EX3 EX2
sbit EWDI  = EIE^4; // Enable Watchdog timer interrupt
sbit EX5   = EIE^3; // External Interrupt 5 Enable.
sbit EX4   = EIE^2; // External Interrupt 4 Enable.
sbit EX3   = EIE^1; // External Interrupt 3 Enable.
sbit EX2   = EIE^0; // External Interrupt 2 Enable.

// EIP: EXTENDED INTERRUPT PRIORITY, - - - PWDI PX5 PX4 PX3 PX2
sbit PWDI  = EIP^4; // Watchdog timer interrupt priority.
sbit PX5   = EIP^3; // External Interrupt 5 Priority. 0 = Low priority, 1 = High priority.
sbit PX4   = EIP^2; // External Interrupt 4 Priority. 0 = Low priority, 1 = High priority.
sbit PX3   = EIP^1; // External Interrupt 3 Priority. 0 = Low priority, 1 = High priority.
sbit PX2   = EIP^0; // External Interrupt 2 Priority. 0 = Low priority, 1 = High priority.