cpu.h

Keil C 51单片机串口通信程序, 通过该程序可以了解和使用单片机串口通信

sbit TH0_5     = TH0^5;
sbit TH0_4     = TH0^4;
sbit TH0_3     = TH0^3;
sbit TH0_2     = TH0^2;
sbit TH0_1     = TH0^1;
sbit TH0_0     = TH0^0;
*/

/*
// TH1: TIMER 1 MSB, TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0
sbit TH1_7     = TH1^7;
sbit TH1_6     = TH1^6;
sbit TH1_5     = TH1^5;
sbit TH1_4     = TH1^4;
sbit TH1_3     = TH1^3;
sbit TH1_2     = TH1^2;
sbit TH1_1     = TH1^1;
sbit TH1_0     = TH1^0;
*/

// P1: PORT 1, P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
sbit P1_7  = P1^7;
sbit P1_6  = P1^6;
sbit P1_5  = P1^5;
sbit P1_4  = P1^4;
sbit P1_3  = P1^3;
sbit P1_2  = P1^2;
sbit P1_1  = P1^1;
sbit P1_0  = P1^0;
/* special function */
sbit T2EX  = P1^1; // 8052 only
sbit T2    = P1^0; // 8052 only

// SCON: SERIAL PORT CONTROL, SM0/FE SM1 SM2 REN TB8 RB8 TI RI
sbit SM0   = SCON^7; // Serial port 0, Mode 0 bit
sbit SM1   = SCON^6; // Serial port Mode bit 1:
					 // 	SM0 SM1  Mode Description  Length  Baudrate
					 //      0   0   0 Synchronous        8    4/12 Tclk
					 //      0   1   1 Asynchronous      10    variable
					 //      1   0   2 Asynchronous      11    64/32 Tclk
					 //      1   1   3 Asynchronous      11    variable
sbit SM2   = SCON^5; // Multiple processors communication. Setting this bit to 1 enables the multiprocessor communication feature in mode 2 and 3. In mode 2 or 3, if SM2 is set to 1, then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1, then RI will not be activated if a valid stop bit was not received. In mode 0, the SM2 bit controls the serial port clock. If set to 0, then the serial port runs at a divide by 12 clock of the oscillator. This gives compatibility with the standard 8052. When set to 1, the serial clock become divide by 4 of the oscillator clock. This results in faster synchronous serial communication.
sbit REN   = SCON^4; // Receive enable: When set to 1 serial reception is enabled, otherwise reception is disabled.
sbit TB8   = SCON^3; // This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared by software as desired.
sbit RB8   = SCON^2; // In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode 0 it has no function.
sbit TI    = SCON^1; // Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in all other modes during serial transmission. This bit must be cleared by software.
sbit RI    = SCON^0; // Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bits time in the other modes during serial reception. However the restrictions of SM2 apply to this bit. This bit can be cleared only by software.
/* special function */
sbit FE    = SCON^7; // Framing Error Flag: The SMOD0 bit in PCON SFR determines whether this bit acts as SM0 or as FE. The operation of SM0 is described below. When used as FE, this bit will be set to indicate an invalid stop bit. This bit must be manually cleared in software to clear the FE condition.

/*
// SBUF: SERIAL DATA BUFFER, SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0
sbit SBUF_7 = SBUF^7;
sbit SBUF_6 = SBUF^6;
sbit SBUF_5 = SBUF^5;
sbit SBUF_4 = SBUF^4;
sbit SBUF_3 = SBUF^3;
sbit SBUF_2 = SBUF^2;
sbit SBUF_1 = SBUF^1;
sbit SBUF_0 = SBUF^0;
*/

// P2: PORT 2, P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
sbit P2_7  = P2^7;
sbit P2_6  = P2^6;
sbit P2_5  = P2^5;
sbit P2_4  = P2^4;
sbit P2_3  = P2^3;
sbit P2_2  = P2^2;
sbit P2_1  = P2^1;
sbit P2_0  = P2^0;

// IE: INTERRUPT ENABLE, EA ES1 ET2 ES ET1 EX1 ET0 EX0
sbit EA    = IE^7; // Global enable. Enable/disable all interrupts except for PFI.
sbit ES1   = IE^6; // WINBOND only, Enable Serial Port 1 interrupt.
sbit ET2   = IE^5; // 8052 only, Enable Timer 2 interrupt.
sbit ES    = IE^4; // Enable Serial Port 0 interrupt.
sbit ET1   = IE^3; // Enable Timer 1 interrupt
sbit EX1   = IE^2; // Enable external interrupt 1
sbit ET0   = IE^1; // Enable Timer 0 interrupt
sbit EX0   = IE^0; // Enable external interrupt 0

// P3: PORT 3, P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
sbit P3_7  = P3^7;
sbit P3_6  = P3^6;
sbit P3_5  = P3^5;
sbit P3_4  = P3^4;
sbit P3_3  = P3^3;
sbit P3_2  = P3^2;
sbit P3_1  = P3^1;
sbit P3_0  = P3^0;

// IP: INTERRUPT PRIORITY, - PS1 PT2 PS PT1 PX1 PT0 PX0
sbit PS1   = IP^6; // WINBOND only, This bit defines the Serial port 1 interrupt priority. PS = 1 sets it to higher priority level.
sbit PT2   = IP^5; // This bit defines the Timer 2 interrupt priority. PT2 = 1 sets it to higher priority level.
sbit PS    = IP^4; // This bit defines the Serial port 0 interrupt priority. PS = 1 sets it to higher priority level.
sbit PT1   = IP^3; // This bit defines the Timer 1 interrupt priority. PT1 = 1 sets it to higher priority level.
sbit PX1   = IP^2; // This bit defines the External interrupt 1 priority. PX1 = 1 sets it to higher priority level.
sbit PT0   = IP^1; // This bit defines the Timer 0 interrupt priority. PT0 = 1 sets it to higher priority level.
sbit PX0   = IP^0; // This bit defines the External interrupt 0 priority. PX0 = 1 sets it to higher priority level.

// PSW: PROGRAM STATUS WORD, CY AC F0 RS1 RS0 OV F1 P
sbit CY    = PSW^7; // Carry flag: Set for an arithmetic operation which results in a carry being generated from the ALU. It is also used as the accumulator for the bit operations.
sbit AC    = PSW^6; // Auxiliary carry: Set when the previous operation resulted in a carry from the high order nibble.
sbit F0    = PSW^5; // User flag 0: General purpose flag that can be set or cleared by the user.
sbit RS1   = PSW^4; // RS.1-0: Register bank select bits: 
sbit RS0   = PSW^3; //         RS1 RS0  Register bank  Address, 
                    //          0   0          0       00-07h, 
                    //          0   1          1       08-0Fh, 
                    //          1   0          2       10-17h, 
                    //          1   1          3       18-1Fh
sbit OV    = PSW^2; // Overflow flag: Set when a carry was generated from the seventh bit but not from the 8th bit as a result of the previous operation, or vice-versa.
sbit F1    = PSW^1; // WINBOND only, User Flag 1: General purpose flag that can be set or cleared by the user by software.
sbit P     = PSW^0; // 8052, Parity flag: Set/cleared by hardware to indicate odd/even number of 1's in the accumulator.

// ACC: ACCUMULATOR, ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0
sbit ACC_7 = ACC^7;
sbit ACC_6 = ACC^6;
sbit ACC_5 = ACC^5;
sbit ACC_4 = ACC^4;
sbit ACC_3 = ACC^3;
sbit ACC_2 = ACC^2;
sbit ACC_1 = ACC^1;
sbit ACC_0 = ACC^0;

// B: B REGISTER, B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0
sbit B_7   = B^7;
sbit B_6   = B^6;
sbit B_5   = B^5;
sbit B_4   = B^4;
sbit B_3   = B^3;
sbit B_2   = B^2;
sbit B_1   = B^1;
sbit B_0   = B^0;
             
/////////////////////           
// 8052 Extensions //
/////////////////////

// T2CON: TIMER 2 CONTROL, TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
sbit TF2    = T2CON^7;
sbit EXF2   = T2CON^6;
sbit RCLK   = T2CON^5;
sbit TCLK   = T2CON^4;
sbit EXEN2  = T2CON^3;
sbit TR2    = T2CON^2;
sbit C_T2   = T2CON^1;
sbit CP_RL2 = T2CON^0;

/*
// T2MOD: TIMER 2 MODE CONTROL, HC5 HC4 HC3 HC2 T2CR - T2OE DCEN
sbit HC5    = T2MOD^7; // Hardware Clear INT5 flag. Setting this bit allows the flag of external interrupt 5 to be automatically cleared by hardware while entering the interrupt service routine.
sbit HC4    = T2MOD^6; // Hardware Clear INT4 flag. Setting this bit allows the flag of external interrupt 4 to be automatically cleared by hardware while entering the interrupt service routine.
sbit HC3    = T2MOD^5; // Hardware Clear INT3 flag. Setting this bit allows the flag of external interrupt 3 to be automatically cleared by hardware while entering the interrupt service routine.
sbit HC2    = T2MOD^4; // Hardware Clear INT2 flag. Setting this bit allows the flag of external interrupt 3 to be automatically cleared by hardware while entering the interrupt service routine.
sbit T2CR   = T2MOD^3; // Timer 2 Capture Reset. In the Timer 2 Capture Mode this bit enables/disables hardware automatically reset Timer 2 while the value in TL2 and TH2 have been transferred into the capture register.
sbit T2OE   = T2MOD^1; // Timer 2 Output Enable. This bit enables/disables the Timer 2 clock out function.
sbit DCEN   = T2MOD^0; // Down Count Enable: This bit, in conjunction with the T2EX pin, controls the direction that timer 2 counts in 16-bit auto-reload mode.
*/

/*
// RCAP2L: TIMER 2 CAPTURE LSB, RCAP2L.7 RCAP2L.6 RCAP2L.5 RCAP2L.4 RCAP2L.3 RCAP2L.2 RCAP2L.1 RCAP2L.0
sbit RCAP2L_7 = RCAP2L^7;
sbit RCAP2L_6 = RCAP2L^6;
sbit RCAP2L_5 = RCAP2L^5;
sbit RCAP2L_4 = RCAP2L^4;
sbit RCAP2L_3 = RCAP2L^3;
sbit RCAP2L_2 = RCAP2L^2;
sbit RCAP2L_1 = RCAP2L^1;
sbit RCAP2L_0 = RCAP2L^0;
*/

/*
// RCAP2H: TIMER 2 CAPTURE MSB, RCAP2H.7 RCAP2H.6 RCAP2H.5 RCAP2H.4 RCAP2H.3 RCAP2H.2 RCAP2H.1 RCAP2H.0
sbit RCAP2H_7 = RCAP2H^7;
sbit RCAP2H_6 = RCAP2H^6;
sbit RCAP2H_5 = RCAP2H^5;
sbit RCAP2H_4 = RCAP2H^4;
sbit RCAP2H_3 = RCAP2H^3;
sbit RCAP2H_2 = RCAP2H^2;
sbit RCAP2H_1 = RCAP2H^1;
sbit RCAP2H_0 = RCAP2H^0;
*/

/*
// TL2: TIMER 2 LSB, TL2.7 TL2.6 TL2.5 TL2.4 TL2.3 TL2.2 TL2.1 TL2.0
sbit TL2_7  = TL2^7;
sbit TL2_6  = TL2^6;