cpu.h

Keil C 51单片机串口通信程序, 通过该程序可以了解和使用单片机串口通信

#include <stdio.h>
#include <ctype.h>
#include <absacc.h>
#include <intrins.h>
#include <math.h>
#include <setjmp.h>
#include <stdarg.h>
#include <stdlib.h>
#include <string.h>

////////////////////
// BYTE Registers //
////////////////////

/* 8051 standard */
sfr P0    = 0x80; // PORT 0, P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
sfr SP    = 0x81; // STACK POINTER, SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0
sfr DPL   = 0x82; // DATA POINTER LOW, DPL.7 DPL.6 DPL.5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0
sfr DPH   = 0x83; // DATA POINTER HIGH, DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0
sfr PCON  = 0x87; // POWER CONTROL, SM0D SMOD0 - - GF1 GF0 PD IDL
sfr TCON  = 0x88; // TIMER CONTROL, TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
sfr TMOD  = 0x89; // TIMER MODE CONTROL, GATE C/T M1 M0 GATE C/T M1 M0
sfr TL0   = 0x8A; // TIMER 0 LSB, TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0
sfr TL1   = 0x8B; // TIMER 1 LSB, TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0
sfr TH0   = 0x8C; // TIMER 0 MSB, TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0
sfr TH1   = 0x8D; // TIMER 1 MSB, TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0
sfr P1    = 0x90; // PORT 1, P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
sfr SCON  = 0x98; // SERIAL PORT CONTROL, SM0/FE SM1 SM2 REN TB8 RB8 TI RI
sfr SBUF  = 0x99; // SERIAL DATA BUFFER, SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0
sfr P2    = 0xA0; // PORT 2, P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
sfr IE    = 0xA8; // INTERRUPT ENABLE, EA ES1 ET2 ES ET1 EX1 ET0 EX0
sfr P3    = 0xB0; // PORT 3, P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
sfr IP    = 0xB8; // INTERRUPT PRIORITY, - PS1 PT2 PS PT1 PX1 PT0 PX0
sfr PSW   = 0xD0; // PROGRAM STATUS WORD, CY AC F0 RS1 RS0 OV F1 P
sfr ACC   = 0xE0; // ACCUMULATOR, ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0
sfr B     = 0xF0; // B REGISTER, B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0

/* 8052 Extensions */
sfr T2CON  = 0xC8; // TIMER 2 CONTROL, TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
sfr T2MOD  = 0xC9; // TIMER 2 MODE CONTROL, HC5 HC4 HC3 HC2 T2CR - T2OE DCEN
sfr RCAP2L = 0xCA; // TIMER 2 CAPTURE LSB, RCAP2L.7 RCAP2L.6 RCAP2L.5 RCAP2L.4 RCAP2L.3 RCAP2L.2 RCAP2L.1 RCAP2L.0
sfr RCAP2H = 0xCB; // TIMER 2 CAPTURE MSB, RCAP2H.7 RCAP2H.6 RCAP2H.5 RCAP2H.4 RCAP2H.3 RCAP2H.2 RCAP2H.1 RCAP2H.0
sfr TL2    = 0xCC; // TIMER 2 LSB, TL2.7 TL2.6 TL2.5 TL2.4 TL2.3 TL2.2 TL2.1 TL2.0
sfr TH2    = 0xCD; // TIMER 2 MSB, TH2.7 TH2.6 TH2.5 TH2.4 TH2.3 TH2.2 TH2.1 TH2.0

/* WinBond extension */
sfr DPL1   = 0x84; // DATA POINTER LOW1, DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0
sfr DPH1   = 0x85; // DATA POINTER HIGH1, DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0
sfr DPS    = 0x86; // DATA POINTER SELECT, - - - - - - - DPS.0
sfr CKCON  = 0x8E; // CLOCK CONTROL, WD1 WD0 T2M T1M T0M MD2 MD1 MD0
sfr EXIF   = 0x91; // EXTERNAL INTERRUPT FLAG, IE5 IE4 IE3 IE2 XT/RG RGMD RGSL -
sfr P4     = 0xA5; // PORT 4, - - - - P4.3 P4.2 P4.1 P4.0

sfr SADDR  = 0xA9; // SLAVE ADDRESS, The SADDR should be programmed to the given or broadcast address for serial port 0 to which the slave processor is designated.
sfr SADDR1 = 0xAA; // SLAVE ADDRESS 1, The SADDR1 should be programmed to the given or broadcast address for serial port 1 to which the slave processor is designated.
sfr SADEN  = 0xB9; // SLAVE ADDRESS MASK ENABLE, This register enables the Automatic Address Recognition feature of the Serial port 0. When a bit in the SADEN is set to 1, the same bit location in SADDR will be compared with the incoming serial data. When SADEN.n is 0, then the bit becomes a "don't care" in the comparison. This register enables the Automatic Address Recognition feature of the Serial port 0. When all the bits of SADEN are 0, interrupt will occur for any incoming address.
sfr SADEN1 = 0xBA; // SLAVE ADDRESS MASK ENABLE 1, This register enables the Automatic Address Recognition feature of the Serial port 1. When a bit in the SADEN1 is set to 1, the same bit location in SADDR1 will be compared with the incoming serial data. When SADEN1.n is 0, then the bit becomes a "don't care" in the comparison. This register enables the Automatic Address Recognition feature of the Serial port 1. When all the bits of SADEN1 are 0, interrupt will occur for any incoming address.
sfr SCON1  = 0xC0; // SERIAL PORT CONTROL 1, SM0_1/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1
sfr SBUF1  = 0xC1; // SERIAL DATA BUFFER 1, SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0
sfr ROMMAP = 0xC2; // ROMMAP, WS 1 - - - - - -
sfr PMR    = 0xC4; // POWER MANAGEMENT REGISTER, CD1 CD0 SWB - XTOFF ALE-OFF - DME0
sfr STATUS = 0xC5; // STATUS REGISTER, - HIP LIP XTUP SPTA1 SPRA1 SPTA0 SPRA0
sfr TA     = 0xC7; // TIMED ACCESS, TA.7 TA.6 TA.5 TA.4 TA.3 TA.2 TA.1 TA.0
sfr WDCON  = 0xD8; // WATCHDOG CONTROL, SMOD_1 POR - - WDIF WTRF EWT RWT
sfr EIE    = 0xE8; // EXTENDED INTERRUPT ENABLE, - - - EWDI EX5 EX4 EX3 EX2
sfr EIP    = 0xF8; // EXTENDED INTERRUPT PRIORITY, - - - PWDI PX5 PX4 PX3 PX2

///////////////////
// BIT Registers //
///////////////////

// P0: PORT 0, P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
sbit P0_7  = P0^7;
sbit P0_6  = P0^6;
sbit P0_5  = P0^5;
sbit P0_4  = P0^4;
sbit P0_3  = P0^3;
sbit P0_2  = P0^2;
sbit P0_1  = P0^1;
sbit P0_0  = P0^0;

/*
// SP: STACK POINTER, SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0
sbit SP_7  = SP^7;
sbit SP_6  = SP^6;
sbit SP_5  = SP^5;
sbit SP_4  = SP^4;
sbit SP_3  = SP^3;
sbit SP_2  = SP^2;
sbit SP_1  = SP^1;
sbit SP_0  = SP^0;
*/

/*
// DPL: DATA POINTER LOW, DPL.7 DPL.6 DPL.5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0
sbit DPL_7 = DPL^7;
sbit DPL_6 = DPL^6;
sbit DPL_5 = DPL^5;
sbit DPL_4 = DPL^4;
sbit DPL_3 = DPL^3;
sbit DPL_2 = DPL^2;
sbit DPL_1 = DPL^1;
sbit DPL_0 = DPL^0;
*/

/*
// DPH: DATA POINTER HIGH, DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0
sbit DPH_7 = DPH^7;
sbit DPH_6 = DPH^6;
sbit DPH_5 = DPH^5;
sbit DPH_4 = DPH^4;
sbit DPH_3 = DPH^3;
sbit DPH_2 = DPH^2;
sbit DPH_1 = DPH^1;
sbit DPH_0 = DPH^0;
*/

/*
// PCON: POWER CONTROL, SM0D SMOD0 - - GF1 GF0 PD IDL
sbit SM0D  = PCON^7; // This bit doubles the serial port baud rate in mode 1, 2, and 3 when set to 1.
sbit SMOD0 = PCON^6; // Framing Error Detection Enable: When SMOD0 is set to 1, then SCON.7(SCON1.7) indicates a Frame Error and acts as the FE(FE_1) flag. When SMOD0 is 0, then SCON.7(SCON1.7) acts as per the standard 8052 function.
sbit GF1   = PCON^3; // These two bits are general purpose user flags.
sbit GF0   = PCON^2; // These two bits are general purpose user flags.
sbit PD    = PCON^1; // Setting this bit causes the W77E58 to go into the POWER DOWN mode. In this mode all the clocks are stopped and program execution is frozen.
sbit IDL   = PCON^0; // Setting this bit causes the W77E58 to go into the IDLE mode. In this mode the clocks to the CPU are stopped, so program execution is frozen. But the clock to the serial, timer and interrupt blocks is not stopped, and these blocks continue operating.
*/

// TCON: TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
sbit TF1   = TCON^7; // Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared automatically when the program does a timer 1 interrupt service routine. Software can also set or clear this bit.
sbit TR1   = TCON^6; // Timer 1 run control: This bit is set or cleared by software to turn timer/counter on or off.
sbit TF0   = TCON^5; // Timer 0 overflow flag: This bit is set when Timer 0 overflows. It is cleared automatically when the program does a timer 0 interrupt service routine. Software can also set or clear this bit.
sbit TR0   = TCON^4; // Timer 0 run control: This bit is set or cleared by software to turn timer/counter on or off.
sbit IE1   = TCON^3; // Interrupt 1 edge detect: Set by hardware when an edge/level is detected on INT1. This bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered. Otherwise it follows the pin.
sbit IT1   = TCON^2; // Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level triggered external inputs.
sbit IE0   = TCON^1; // Interrupt 0 edge detect: Set by hardware when an edge/level is detected on INT0 . This bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered. Otherwise it follows the pin.
sbit IT0   = TCON^0; // Interrupt 0 type control: Set/cleared by software to specify falling edge/ low level triggered external inputs.

/*
// TMOD: TIMER MODE CONTROL, GATE C/T M1 M0 GATE C/T M1 M0
sbit T1_GATE  = TMOD^7; // Gating control: When this bit is set, Timer/counter x is enabled only while INTx pin is high and TRx control bit is set. When cleared, Timer x is enabled whenever TRx control bit is set.
sbit T1_CT    = TMOD^6; // Timer or Counter Select: When cleared, the timer is incremented by internal clocks. When set, the timer counts high-to-low edges of the Tx pin.
sbit T1_M1    = TMOD^5; // M1, M0: Mode Select bits: 
sbit T1_M0    = TMOD^4; // M1 M0 Mode
						// 0  0  Mode 0: 8-bits with 5-bit prescale.
						// 0  1  Mode 1: 18-bits, no prescale.
						// 1  0  Mode 2: 8-bits with auto-reload from THx
						// 1  1  Mode 3: (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer 0
						// control bits. TH0 is a 8-bit timer only controlled by Timer 1 control bits. (Timer 1) Timer/counter is stopped.
sbit T0_GATE  = TMOD^3; // Gating control: When this bit is set, Timer/counter x is enabled only while INTx pin is high and TRx control bit is set. When cleared, Timer x is enabled whenever TRx control bit is set.
sbit T0_CT    = TMOD^2; // Timer or Counter Select: When cleared, the timer is incremented by internal clocks. When set, the timer counts high-to-low edges of the Tx pin.
sbit T0_M1    = TMOD^1; // M1, M0: Mode Select bits: 
sbit T0_M0    = TMOD^0; // M1 M0 Mode
						// 0  0  Mode 0: 8-bits with 5-bit prescale.
						// 0  1  Mode 1: 18-bits, no prescale.
						// 1  0  Mode 2: 8-bits with auto-reload from THx
						// 1  1  Mode 3: (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer 0
						// control bits. TH0 is a 8-bit timer only controlled by Timer 1 control bits. (Timer 1) Timer/counter is stopped.
*/

/*					
// TL0: TIMER 0 LSB, TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0
sbit TL0_7     = TL0^7;
sbit TL0_6     = TL0^6;
sbit TL0_5     = TL0^5;
sbit TL0_4     = TL0^4;
sbit TL0_3     = TL0^3;
sbit TL0_2     = TL0^2;
sbit TL0_1     = TL0^1;
sbit TL0_0     = TL0^0;
*/

/*
// TL1: TIMER 1 LSB, TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0
sbit TL1_7     = TL1^7;
sbit TL1_6     = TL1^6;
sbit TL1_5     = TL1^5;
sbit TL1_4     = TL1^4;
sbit TL1_3     = TL1^3;
sbit TL1_2     = TL1^2;
sbit TL1_1     = TL1^1;
sbit TL1_0     = TL1^0;
*/

/*
// TH0: TIMER 0 MSB, TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0
sbit TH0_7     = TH0^7;
sbit TH0_6     = TH0^6;