spi.asm

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*********************************************************************
* Filename SPI.ASM ----- TMS320C54x code for accessing SPI EEPROMs  *
* Author: Ruben D. Perez                                  06/15/99  *
*********************************************************************
* This file includes subroutines which can be used to access a SPI  *
* based serial EEPROM with the multi-channel buffered serial port   *
* (McBSP) of the C5000 generation of TI DSPs. The routines can be   *
* used with any McBSP, since two pointers to the McBSP registers    *
* (AR4 and AR5) must be passed when calling the routines. See the   *
* comments at the top of each routine for more details. The code is *
* intended for use with byte-wide serial EEPROMs. Although most SPI *
* based EEPROMs include the same compatible interface, this code has*
* only been tested with the following devices:                      *
* Microchip 25AA640                                                 *
* Some modification may be required for use with other EEPROMs.     *
*********************************************************************
* Known Limitaions:                                                 *
* - This code supports single byte reads and writes only. The reason*
*   is that SPI EEPROMs require an active chip-select throughout a  *
*   multi-byte read or write operation, and the McBSP frame sync    *
*   doesn't support this.                                           *
* - This code uses polling which is MIPs intensive and inefficient. *
*   It can be modified to use interrupts or even DMA.               * 
*********************************************************************
* Revision 0.0, 01/04/99                                            *
* Revision 1.0  06/15/99 Ruben D. Perez Corrected a clock phase     *
*                        problem by changing the SPI_INIT routine   *
*                        to configure SPCR1:CLKSTP=11b instead of   *
*                        10b, and PCR:CLKRP=1 instead of 0.         *
* The following subroutines are implemented:                        *
* SPI_INIT  - Initializes the McBSP for 32-bit SPI master mode.     *
* SPI_READ  - Reads a byte from the specified address.              *
* SPI_WRITE - Writes the specified byte to the specified address.   *
* SPI_RDSR  - Reads the EEPROM status register.                     *
* SPI_WRSR  - Writes the EEPROM status register.                    *
*********************************************************************
                .def    SPI_INIT, SPI_READ, SPI_WRITE
                .def    SPI_RDSR, SPI_WRSR
                        

*********************************************************************
* Constants                                                         *
*********************************************************************
**********SPI EEPROM COMMANDS****************************************
*********************************************************************
WREN            .set    06h      ;Set Write Enable Latch            
WRDI            .set    04h      ;Reset Write Enable Latch          
RDSR            .set    05h      ;Read Status Register              
WRSR            .set    01h      ;Write Status Register             
READ            .set    03h      ;Read Data from Memory Array       
WRITE           .set    02h      ;Write Data to Memory Array        
*********************************************************************

*********************************************************************
* SCLKDIV This constant (1 to 255) should be >= to the bit rate     *
*         divisor CLKGDV. It is used by the DELAY2B subroutine, to  *
*         generate a 2-bit delay for settling time during McBSP     *
*         initialization.                                           *
*********************************************************************
SCLKDIV         .set    250     ;Running very slow for a 1.8V EEPROM
*********************************************************************



*********************************************************************
*******McBSP Sub-bank addressed registers****************************           
*********************************************************************
SPCR1_sub       .set    00h     ;Serial Port Control Register 1.
SPCR2_sub       .set    01h     ;Serial Port Control Register 2.
RCR1_sub        .set    02h     ;Recieve Control Register 1.
RCR2_sub        .set    03h     ;Recieve Control Register 2.
XCR1_sub        .set    04h     ;Transmit Control Register 1.
XCR2_sub        .set    05h     ;Transmit Control Register 2.
SRGR1_sub       .set    06h     ;Sample Rate Generator Register 1.
SRGR2_sub       .set    07h     ;Sample Rate Generator Register 2.
PCR_sub         .set    0Eh     ;Pin Control Register.
*********************************************************************


        .sect ".spi"

*********************************************************************
* SPI_INIT - This routine is used to initialize the McBSP for use   *
* as a SPI master. SPI mode0 (CLKSTP=10, CLKXP=0) is selected. The  *
* following registers are used:                                     *
*    A   - The clock divisor (CLKGDV) is passed in A.               *
*          SPI bitrate = CPU freq/( CLKGDV + 1 ), CLKGDV:[1,255]    *
*    AR4 - Must point to serial port sub-bank address reg (SPSA).   *
*********************************************************************
SPI_INIT
**** Init transmitter************************************************
        ST      #SPCR1_sub, *AR4+ ;Sub-bank Address (SPSA) = SPCR1.
        ST      #1800h, *AR4-     ;Reset xmiter and enable clkstp=11b.
        ST      #XCR1_sub, *AR4+  ;Set Sub-bank Address to XCR1.
        ST      #0A0h, *AR4-      ;Select 32-bit packets for xmit.
        ST      #XCR2_sub, *AR4+  ;Set Sub-bank Address to XCR2.
        ST      #1h, *AR4-        ;Select 1bit delay for xmit.
**** Init reciever **************************************************
        ST      #SPCR2_sub, *AR4+ ;Set Sub-bank Address to SPCR2.
        ST      #0200h, *AR4-     ;Reset rcvr and clk gen, FREE=1 .#1
        ST      #RCR1_sub, *AR4+  ;Set Sub-bank Address to RCR1.
        ST      #0A0h, *AR4-      ;Select 32-bit packets for rcv.
        ST      #RCR2_sub, *AR4+  ;Set Sub-bank Address to RCR2.
        ST      #1h, *AR4-        ;Select 1bit delay for rcv.
**** Init bit rate and frame generator ******************************
        ST      #SRGR1_sub, *AR4+ ;Set Sub-bank Address to SRGR1.
        STL     A, *AR4-          ;bit rate=sysclk/(accuA+1).
        ST      #SRGR2_sub, *AR4+ ;Set Sub-bank Address to SRGR2.
        ST      #2000h, *AR4-     ;Configure frames.
        CALL    DELAY2B           ;Delay for 2bit clocks.
*** Start clock generator *******************************************
        ST      #SPCR2_sub, *AR4+ ;Set Sub-bank Address to SPCR2.
        ST      #0240h, *AR4-     ;Take clk gen out of reset.    #1.5
        CALL    DELAY2B           ;Delay for 2bit clocks.
*** Configure pin directions and polarities *************************
        ST      #PCR_sub, *AR4+   ;Set Sub-bank Address to PCR.
        ST      #0A0Dh, *AR4-     ;CLKXM=1/FSXM=1/CLKXP=0/CLKRP=1
                                  ;FSRP=FSXP=1.                    #2
        CALL    DELAY2B           ;Delay for 2bit clocks.
*** Enable clock-stop mode (100) and enable rcvr/xmitr **************
        ST      #SPCR1_sub, *AR4+ ;Set Sub-bank Address to SPCR1.        
        ST      #01801h, *AR4-    ;Enable McBSP transmitter.       #5
        ST      #SPCR2_sub, *AR4+ ;Set Sub-bank Address to SPCR2.
        ST      #0241h, *AR4-     ;Enable McBSP reciever.          #5
        CALL    DELAY2B           ;Delay for 2bit clocks.
        RET

*********************************************************************
* SPI_READ - This subroutine is used to read a byte from the EEPROM.*
* The following registers are used:                                 *
*                                                                   *
*    A   - The data read is returned in accu A.                     * 
*    AR3 - The address to read from is passed in AR3.               *
*    AR4 - Must point to serial port sub-bank address reg (SPSA)    *
*    AR5 - Must point to data transmit register2 (DXR2x).           *
*********************************************************************
SPI_READ
        LD      #READ, 16, B      ;Get read command.
        B       SPI_CMD           ;Re-use SPI_CMD subroutine.

*********************************************************************
* SPI_RDSR - This subroutine is used to read the EEPROM status reg. *
* The following registers are used:                                 *
*                                                                   *
*    A   - The data read is returned in accu A.                     * 
*    AR4 - Must point to serial port sub-bank address reg (SPSA).   *
*    AR5 - Must point to data transmit register2 (DXR2x).           *
*********************************************************************
SPI_RDSR