📄 boot5402.lst
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349 0000c2 1262 ldu @entry,a ; branch to the entry point
350 0000c3 3C61 add @xentry,16,a ;
351 0000c4 F4E6 hpiboot fbacc a
352
353 *****************************************************************
354 * Bootload from 8-bit memory, MS byte first
355 *****************************************************************
356
357 0000c5 par08
358 0000c5 6F91 ld *ar1+, 8, a ; read MSB of SWWSR value
TMS320C54x COFF Assembler Version 3.50 Thu Feb 03 13:21:23 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
bootVC5402 PAGE 9
0000c6 0C48
359 0000c7 7191 mvdk *ar1+, ar3 ; read LSB of SWWSR value
0000c8 0013
360 0000c9 6813 andm #0ffh, @ar3 ; Mask off upper 8-bits
0000ca 00FF
361 0000cb 1A13 or @ar3, a ; Concatenate
362 0000cc 8828 stlm a,swwsr ; store A to SWWSR
363
364 0000cd 6F91 ld *ar1+, 8, a ; read MSB of BSCR value
0000ce 0C48
365 0000cf 7191 mvdk *ar1+, ar3 ; read LSB of BSCR value
0000d0 0013
366 0000d1 6813 andm #0ffh, @ar3 ; Mask off upper 8-bits
0000d2 00FF
367 0000d3 1A13 or @ar3, a ; Concatenate
368 0000d4 8829 stlm a,bscr ; store A to BSCR
369
370 0000d5 6F91 ld *ar1+, 8, a ; read MSB of XPC of entry addr
0000d6 0C48
371 0000d7 7191 mvdk *ar1+, ar3 ; read LSB
0000d8 0013
372 0000d9 6813 andm #0ffh, @ar3 ; Mask off upper 8-bits
0000da 00FF
373 0000db 1A13 or @ar3, a ; Concatenate
374 0000dc 8061 stl a,@xentry ; stor A to xentry
375
376 0000dd 6F91 ld *ar1+, 8, a ; read MSB of entry address
0000de 0C48
377 0000df 7191 mvdk *ar1+, ar3 ; read LSB
0000e0 0013
378 0000e1 6813 andm #0ffh, @ar3 ; Mask off upper 8-bits
0000e2 00FF
379 0000e3 1A13 or @ar3, a ; Concatenate
380 0000e4 8062 stl a,@entry ; stor A to entry
381
382 0000e5 6F91 par08_1 ld *ar1+, 8, a ; get MSB of block size (16-bit words)
0000e6 0C48
383 0000e7 F030 and #0ff00h, a ; Clear grd bits, and upper word. Rev1.01
0000e8 FF00
384 0000e9 7191 mvdk *ar1+, ar3 ; read LSB
0000ea 0013
385 0000eb 6813 andm #0ffh, @ar3 ; Mask off upper 8-bits
0000ec 00FF
386 0000ed 1A13 or @ar3, a ; Concatenate
387 0000ee FA45 bcd endboot,aeq ; section size =0 indicate boot end
0000ef 00C2+
388 0000f0 F110 sub #1,a,b ; brc = section size - 1
0000f1 0001
389 0000f2 891A stlm b, brc ; update block repeat counter register
390
391 0000f3 6F91 ld *ar1+, 8, a ; get MSB of XPC of destination
0000f4 0C48
392 0000f5 7191 mvdk *ar1+, ar3 ; read LSB
0000f6 0013
393 0000f7 6813 andm #0ffh, @ar3 ; Mask off upper 8-bits
TMS320C54x COFF Assembler Version 3.50 Thu Feb 03 13:21:23 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
bootVC5402 PAGE 10
0000f8 00FF
394 0000f9 1A13 or @ar3, a ; Concatenate
395 0000fa 8066 stl a,@dest ; @dest <-- XPC
396
397 0000fb 6F91 ld *ar1+, 8, a ; get MSB of destinationaddress
0000fc 0C48
398 ************* Bug fix ******************************************************
399 0000fd F030 and #0ff00h,a ;force AG, AH to zero for correct calculation
0000fe FF00
400 ;of the 23-bit destination address.
401 ;(11/10/99 PMJ2) 1.03
402 ****************************************************************************
403 0000ff 7191 mvdk *ar1+, ar3 ; read LSB
000100 0013
404 000101 6813 andm #0ffh, @ar3 ; Mask off upper 8-bits
000102 00FF
405 000103 1A13 or @ar3, a ; Concatenate
406 000104 3C66 add @dest,16,a ; acc A <-- 23-bit destination address
407
408 000105 F072 rptb xfr08-1
000106 0112+
409 000107 6F91 ld *ar1+, 8, b ; read MSB of data
000108 0D48
410 000109 7191 mvdk *ar1+, ar3 ; read LSB of data
00010a 0013
411 00010b 6813 andm #0ffh, @ar3 ; Mask off upper 8-bits
00010c 00FF
412 00010d 1B13 or @ar3, b ; Concatenate
413
414 00010e EC0A rpt #10 ;insert at least 10 cycles
415 00010f F495 nop ; between read and write
416
417 000110 7F0B writa BL ; write object data to destination
418 000111 F000 add #1, a ; increment destination address
000112 0001
419
420 000113 xfr08
421 000113 F073 b par08_1
000114 00E5+
422
423 *****************************************************************
424 * Bootload from 16-bit memory
425 *****************************************************************
426
427 000115 par16
428 000115 1091 ld *ar1+, a ; read desired value of SWWSR
429 000116 8828 stlm a, @swwsr ; store in SWWSR
430
431 000117 1091 ld *ar1+, a ; read desired value of BSCR
432 000118 F030 and #0FFFEh,a ; ensure EXIO bit is off
000119 FFFE
433 00011a 8829 stlm a, @bscr ; store in BSCR
434
435 00011b 1091 ld *ar1+, a ; read XPC of entry point address
436 00011c 8061 stl a, @xentry ; and store
TMS320C54x COFF Assembler Version 3.50 Thu Feb 03 13:21:23 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
bootVC5402 PAGE 11
437
438 00011d 1091 ld *ar1+, a ; read low 16-bits of entry point addr
439 00011e 8062 stl a, @entry ; and store
440
441 00011f 1091 par16_1 ld *ar1+,a ; load the size of section to A
442 000120 FA45 bcd endboot,aeq ; section size =0 indicate boot end
000121 00C2+
443 000122 F110 sub #1,a,b ; brc = section size - 1
000123 0001
444 000124 891A stlm b, brc ; update BRC
445
446 000125 1091 ld *ar1+,a ; get the XPC of destination (A22-A16)
447 000126 8066 stl a,@dest ; store XPC at data memory @dest
448 000127 1291 ldu *ar1+,a ; get address of destination in A(15-0)
449 000128 8812 stlm a,ar2 ; store dest address at ar2
450 000129 3C66 add @dest,16,a ; acc A <--- 23-bit destination address
451
452 00012a F072 rptb xfr16-1
00012b 0132+
453 00012c 7191 mvdk *ar1+, ar3 ; read object data
00012d 0013
454
455 00012e EC0A rpt #10 ;insert at least 10 cycles
456 00012f F495 nop ; between read and write
457
458 000130 7F13 writa @ar3 ; write object data to destination
459 000131 F000 add #1,a ;increment desintation address
000132 0001
460 000133 xfr16
461 000133 F073 b par16_1
000134 011F+
462
463
464 *****************************************************************
465 * Bootload from BSP serial port
466 *****************************************************************
467
468 000135 ser_in
469 000135 F4BC rsbx tc ; clear flag
470 000136 FA20 bcd $, ntc ; begin receive data routine
000137 0136+
471 000138 6186 BITF *AR6,#0002h ; Bit test on RRDY. Reception of a new word.
000139 0002
472 00013a FC00 RET
473
474 00013b BSP0
475 00013b 7738 STM SPCR1_SUBADDR,SPSA0 ; Set up to read the value of the
00013c 0000
476 00013d 7716 STM SPSD0,AR6 ; SPCR10 reg, RRDY.
00013e 0039
477 00013f 7711 stm #drr10,ar1 ; ar1 <-- drr0
000140 0021
478 000141 7701 stm #010h, @ifr ; clear BRINT0 flag
000142 0010
479 000143 F073 b SP_in_16 ; check BSP
TMS320C54x COFF Assembler Version 3.50 Thu Feb 03 13:21:23 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
bootVC5402 PAGE 12
000144 014F+
480 000145 BSP1
481 000145 7748 STM SPCR1_SUBADDR,SPSA1 ; Set up to read the value of the
000146 0000
482 000147 7716 STM SPSD1,AR6 ; SPCR10 reg, RRDY.
000148 0049
483 000149 7711 stm #drr11,ar1 ; ar1 <-- drr0
00014a 0041
484 00014b 7701 stm #400h, @ifr ; clear BRINT1 flag
00014c 0400
485 00014d F073 b SP_in_8 ; check BSP
00014e 0195+
486
487
488 *****************************************************************
489 * McBSP Bootload in 16-bit mode *
490 *****************************************************************
491
492 00014f SP_in_16
493 00014f 4881 ldm *ar1, a ; acc A <-- DRR
494 000150 F110 sub #10AAh, a, b ; acc A = 0x10AA ?
000151 10AA
495 000152 F84D bc ser_in_16, beq ; 16-bit serial mode
000153 0155+
496 000154 FC00 ret
497
498 000155 ser_in_16
499 ;The dummy words are read to maintain
500 ; hex converter compatibility with
501 ; the 548/549
502
503 000155 F074 call ser_in ; call SP input sub
000156 0135+
504 000157 7181 mvdk *ar1, temp0 ; temp0 <-- drr0 (DUMMY WORD)
000158 0069
505 000159 F074 call ser_in ; call SP input sub
00015a 0135+
506 00015b 7181 mvdk *ar1, temp1 ; temp1 <-- drr0 (DUMMY WORD)
00015c 006A
507 00015d F074 call ser_in ; call SP input sub
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