📄 boot5402.lst
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TMS320C54x COFF Assembler Version 3.50 Thu Feb 03 13:21:23 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
bootVC5402 PAGE 1
1 *************************************************************************
2 ***
3 *** VC5402 Bootloader Software : Version 1.03
4 *** Origin Date : 9/30/98
5 *** Author(s) : RDP
6 ***
7 *************************************************************************
8 ***
9 *** This code sets up and executes the VC5402 Bootloader.
10 ***
11 *** Revision History:
12 *** ----------------
13 *** 1.00 Modified the VC5410 bootloader for use RDP 09/30/98
14 *** on the VC5402. Added new HPI boot mode,
15 *** and removed McBSP2 code. See notes on
16 *** HPI boot mode below.
17 *** 1.01 Fixed bug in 8bit parallel mode, by RDP 11/12/98
18 *** masking off the upper ACCUA bits of
19 *** the word containing the upper byte
20 *** of the section size.
21 *** 1.02 Fixed the 8bit standard serial mode, RDP 02/26/99
22 *** by changing the initialization of RCR11
23 *** and XCR11 from 040h to 0h.
24 *** Added a SPI EEPROM bootmode, which is
25 *** selected via the INT3 flag (See notes
26 *** on SPI boot mode below). Changed the
27 *** references to the McBSP control
28 *** registers to emphasize the sub-bank
29 *** addressing scheme. Added more comments,
30 *** and cleaned-up spacing on older code.
31 *** Fixed a bug in 8-bit I/O mode, by loading
32 *** the top of B with zero. Added code to
33 *** toggle the BDX1 pin during init, to
34 *** provide a high-to-low transition that
35 *** can be used to drive INT3 for selection
36 *** of the SPI boot mode.
37 *** 1.03 Modified Parallel 8-bit. PMJ2 12/06/99
38 *** Modified I/O 8-bit boot modes.
39 *** In the parallel 8-bit mode, the AG and AH
40 *** are forced to zero for correct evaluation.
41 *** In the 8-bit I/O mode, the XPC
42 *** destination addr is correclty saved.
43 *** The BG and BH are forced to zero
44 *** for correct evaluation. The SPI mode boot
45 *** branches to the parallel boot after failure
46 *** of the first condition (08) and second condition (AA).
47 *** Reset McBSP1 before DX pins toggles. (for debugging)
48 ***
49 *************************************************************************
50 *** --------------- Notes on '5402 HPI Boot Mode ---------------
51 *** The new HPI boot mode allows the host to load the on-chip RAM
52 *** after the '5402 is reset. The boot-mode also allows the host
53 *** to specify an entry point at load-time. After completing the
54 *** bootload process, the host must make another HPI access to load
55 *** the entry point to location 07Fh of on-chip RAM. This is how it
TMS320C54x COFF Assembler Version 3.50 Thu Feb 03 13:21:23 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
bootVC5402 PAGE 2
56 *** works: after reset, the bootloader initializes address 07Fh to
57 *** zero, then polls this location for a change while the host is
58 *** loading the code. When the bootloader detects a change in the
59 *** contents of address 07Fh, it performs a branch using the contents
60 *** as the destination address.
61 *** This new mode doesn't require the INT2 flag for selection. If the
62 *** INT2 pin is not used to select HPI boot mode, the bootloader
63 *** periodically checks various boot sources, including HPI, until a
64 *** boot condition is detected. Alternatively, the INT2 flag can be
65 *** used to force the bootloader to ignore all boot sources other
66 *** than HPI. If the INT2 flag is to be used, a high to low transition
67 *** is required on the INT2 pin within 30 cycles after the '5402 is
68 *** reset.
69 *************************************************************************
70 *** --------------- Notes on '5402 SPI Boot Mode ---------------
71 *** The SPI boot mode allows the '5402 to boot from an 8-bit serial
72 *** EEPROM using the SPI protocol. The mode is selected at reset via
73 *** the INT3 external interrupt . Proper selection of the boot mode
74 *** requires a high to low transition on the INT3 pin within 30 CPU
75 *** cycles after the '5402 is reset.
76 ***
77 *** The EEPROM must be connected to McBSP1 as follows:
78 *** McBSP1 EEPROM
79 *** ****** ******
80 *** BCLKX SCK
81 *** BFSX /CS
82 *** BDX SI
83 *** BDR SO
84 *** XF /HOLD (Optional - disables EEPROM when done)
85 ***
86 *** The boot table used for programming the EEPROM is generated
87 *** using the 8bit serial option of the Hex conversion utility.
88 *** example:
89 *** -bootorg SERIAL
90 *** -memwidth 8
91 *************************************************************************
92
93
95 .mmregs
96 .version 548
97 .def boot
98 .def endboot
99 .def bootend
100 .def dest
101 .def src
102 .def lngth
103 .def hbyte
104 .ref SPI_INIT, SPI_READ, SPI_WRITE
105 .ref SPI_RDSR, SPI_WRSR
106
107 *************************************
108 0000 pa0 .set 0H ; port address 0h for i/o boot load
109
110 0061 xentry .set 61H ; XPC of entry point
111 0062 entry .set 62H ; entry point
TMS320C54x COFF Assembler Version 3.50 Thu Feb 03 13:21:23 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
bootVC5402 PAGE 3
112 0063 hbyte .set 63H ; high byte of 8-bit serial word
113 0064 p8word .set 64H ; concatenator for 8-bit memory load
114 0065 src .set 65H ; source address
115 0066 dest .set 66H ; destination address (dmov from above)
116 0067 xdest .set 67H ; XPC of destination address.
117 0068 lngth .set 68H ; code length
118 0069 temp0 .set 69H ; temporary register0
119 006A temp1 .set 6aH ; temporary register1
120 006B temp2 .set 6bH ; temporary register2
121 006C temp3 .set 6cH ; temporary register3
122
123 007F HPIentry .set 7Fh ; Entry point for HPI boot.
124
125 ***********************************************
126 * MMR definition for c54xlp peripherals *
127 *------------- MCBSP0 ----------------------*
128 0021 drr10 .set 21H ; Data Receive Register
129 0023 dxr10 .set 23H ; Data Transmit Register
130 0038 SPSA0 .set 0038H ; Serial Port 0 Sub-bank Address Register
131 0039 SPSD0 .set 0039H ; Serial Port 0 Sub-bank Data Register
132
133
134 *------------- MCBSP1 ----------------------*
135 0041 drr11 .set 41H ; Data Receive Register
136 0043 dxr11 .set 43H ; Data Transmit Register
137 0048 SPSA1 .set 0048H ; Serial Port 1 Sub-bank Address Register
138 0049 SPSD1 .set 0049H ; Serial Port 1 Sub-bank Data Register
139
140 *----------- MCBSP CONTROL REGS --------------*
141 0000 SPCR1_SUBADDR .set 0000H ; Serial Port Control Register 1 (subaddress)
142 0001 SPCR2_SUBADDR .set 0001H ; Serial Port 1 Control Register 2 (subaddress)
143 0002 RCR1_SUBADDR .set 0002H ; Receive Control Register 1 (subaddress)
144 0003 RCR2_SUBADDR .set 0003H ; Receive Control Register 2 (subaddress)
145 0004 XCR1_SUBADDR .set 0004H ; Transmit Control Register 1 (subaddress)
146 0005 XCR2_SUBADDR .set 0005H ; Transmit Control Register 2 (subaddress)
147 0006 SRGR1_SUBADDR .set 0006H ; Sample Rate Genarator Register 1 (subaddress)
148 0007 SRGR2_SUBADDR .set 0007H ; Sample Rate Genarator Register 2 (subaddress)
149 000E PCR_SUBADDR .set 000EH ; Pin Control Register (subaddress)
150
151 *-------------- Other contants ---------------*
152 0004 int2msk .set 0004H ; INT2_ bit position on IFR
153 0100 int3msk .set 0100H ; INT3_ bit position in IFR/IMR
154
155 **********************************************************
156 * bootloader
157 **********************************************************
158 000000 .sect "boot"
159 000000 boot
160
161 000000 F7BB ssbx intm ; disable all interrupts
162 000001 7701 stm #0FFFFh,@ifr ; clear IFR flag
000002 FFFF
163 000003 EA00 ld #0, dp
164 000004 6907 orm #02b00h, @st1 ; xf=1, hm=0, intm=1, ovm=1, sxm=1
000005 2B00
TMS320C54x COFF Assembler Version 3.50 Thu Feb 03 13:21:23 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
bootVC5402 PAGE 4
165 000006 691D orm #020h, @pmst ; ovly=1
000007 0020
166 000008 7728 stm #07fffh, swwsr ; 7 wait states for P_,D_, and I_ spaces
000009 7FFF
167 00000a 7718 stm #0007dh, sp ; Use top part of scratch-pad RAM for stack.
00000b 007D
168
169 *****************************************************************
170 * RDP, Modified old HPI boot check to support host loading
171 * after reset. Initialize HPI boot entry point to 0. The host
172 * will change the value of this location after loading RAM.
173 *****************************************************************
174 00000c 777F stm #0, @HPIentry ; Set HPI entry to known value.
00000d 0000
175 00000e 772C stm #08h, hpic ; Set HINT pin low. Ok to start
00000f 0008
176 ; host load.
177 *****************************************************************
178 * Toggling the BDX pin on McBSP1. This pin can be used to
179 * drive /INT3 and select the SPI boot mode, without requiring
180 * an external signal.
181 *****************************************************************
182
183 000010 7748 STM SPCR2_SUBADDR,SPSA1
000011 0001
184 000012 7749 STM #0000h,SPSD1 ; DISABLES TRANSMIT. (reset) 1.03
000013 0000
185
186 000014 7748 stm #PCR_SUBADDR, SPSA1
000015 000E
187 000016 7749 stm #02020h, SPSD1 ; Set DX high.
000017 2020
188 000018 EC05 rpt #5 ; Keep high a while.
189 000019 F495 nop
190 00001a 7749 stm #02000h, SPSD1 ; Set DX low.
00001b 2000
191
192 00001c EC05 rpt #5 ; wait several cycles
193 00001d F495 nop ; before checking INT2
194 00001e 6101 bitf @ifr, #int2msk ; Check if INT2_ flag is set
00001f 0004
195 000020 F495 nop
196 000021 F830 bc HPI, tc ; If int2 is set then HPI boot.
000022 002A+
197
198 000023 6101 bitf @ifr, #int3msk ; Else, check if INT3_ flag is set
000024 0100
199 000025 F495 nop
200 000026 F830 bc SPIBOOT, tc ; If int3 is set then SPI boot.
000027 01D2+
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