📄 mx2.h
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//# $1002_4000 to $1002_5FFF #
//#########################################
#define OTG_BASE_ADDR 0x10024000
#define OTG_CORE_BASE (OTG_BASE_ADDR+0x000) // base location for core
#define OTG_FUNC_BASE (OTG_BASE_ADDR+0x040) // base location for function
#define OTG_HOST_BASE (OTG_BASE_ADDR+0x080) // base location for host
#define OTG_I2C_BASE (OTG_BASE_ADDR+0x100) // base location for I2C
#define OTG_DMA_BASE (OTG_BASE_ADDR+0x800) // base location for dma
#define OTG_ETD_BASE (OTG_BASE_ADDR+0x200) // base location for etd memory
#define OTG_EP_BASE (OTG_BASE_ADDR+0x400) // base location for ep memory
#define OTG_SYS_BASE (OTG_BASE_ADDR+0x600) // base location for system
#define OTG_DATA_BASE (OTG_BASE_ADDR+0x1000) // base location for data memory
#define OTG_SYS_CTRL (OTG_SYS_BASE+0x000) // base location for system
#define _reg_OTG_CORE_HWMODE (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_CORE_BASE+0x00)))) // 32bit core hardware mode reg
#define _reg_OTG_CORE_CINT_STAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_CORE_BASE+0x04)))) // 32bit core int status reg
#define _reg_OTG_CORE_CINT_STEN (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_CORE_BASE+0x08)))) // 32bit core int enable reg
#define _reg_OTG_CORE_CLK_CTRL (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_CORE_BASE+0x0C)))) // 32bit core clock control reg
#define _reg_OTG_CORE_RST_CTRL (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_CORE_BASE+0x10)))) // 32bit core reset control reg
#define _reg_OTG_CORE_FRM_INTVL (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_CORE_BASE+0x14)))) // 32bit core frame interval reg
#define _reg_OTG_CORE_FRM_REMAIN (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_CORE_BASE+0x18)))) // 32bit core frame remaining reg
#define _reg_OTG_CORE_HNP_CSTAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_CORE_BASE+0x1C)))) // 32bit core HNP current state reg
#define _reg_OTG_CORE_HNP_TIMER1 (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_CORE_BASE+0x20)))) // 32bit core HNP timer 1 reg
#define _reg_OTG_CORE_HNP_TIMER2 (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_CORE_BASE+0x24)))) // 32bit core HNP timer 2 reg
#define _reg_OTG_CORE_HNP_T3PCR (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_CORE_BASE+0x28)))) // 32bit core HNP timer 3 pulse ctrl
#define _reg_OTG_CORE_HINT_STAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_CORE_BASE+0x2C)))) // 32bit core HNP int status reg
#define _reg_OTG_CORE_HINT_STEN (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_CORE_BASE+0x30)))) // 32bit core HNP int enable reg
#define _reg_OTG_FUNC_CND_STAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_FUNC_BASE+0x00)))) // 32bit func command status reg
#define _reg_OTG_FUNC_DEV_ADDR (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_FUNC_BASE+0x04)))) // 32bit func device address reg
#define _reg_OTG_FUNC_SINT_STAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_FUNC_BASE+0x08)))) // 32bit func system int status reg
#define _reg_OTG_FUNC_SINT_STEN (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_FUNC_BASE+0x0C)))) // 32bit func system int enable reg
#define _reg_OTG_FUNC_XINT_STAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_FUNC_BASE+0x10)))) // 32bit func X buf int status reg
#define _reg_OTG_FUNC_YINT_STAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_FUNC_BASE+0x14)))) // 32bit func Y buf int status reg
#define _reg_OTG_FUNC_XYINT_STEN (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_FUNC_BASE+0x18)))) // 32bit func XY buf int enable reg
#define _reg_OTG_FUNC_XFILL_STAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_FUNC_BASE+0x1C)))) // 32bit func X filled status reg
#define _reg_OTG_FUNC_YFILL_STAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_FUNC_BASE+0x20)))) // 32bit func Y filled status reg
#define _reg_OTG_FUNC_EP_EN (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_FUNC_BASE+0x24)))) // 32bit func endpoints enable reg
#define _reg_OTG_FUNC_EP_RDY (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_FUNC_BASE+0x28)))) // 32bit func endpoints ready reg
#define _reg_OTG_FUNC_IINT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_FUNC_BASE+0x2C)))) // 32bit func immediate interrupt reg
#define _reg_OTG_FUNC_EP_DSTAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_FUNC_BASE+0x30)))) // 32bit func endpoints done status
#define _reg_OTG_FUNC_EP_DEN (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_FUNC_BASE+0x34)))) // 32bit func endpoints done enable
#define _reg_OTG_FUNC_EP_TOGGLE (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_FUNC_BASE+0x38)))) // 32bit func endpoints toggle bits
#define _reg_OTG_FUNC_FRM_NUM (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_FUNC_BASE+0x3C)))) // 32bit func frame number reg
#define _reg_OTG_HOST_CTRL (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x00)))) // 32bit host controller config reg
#define _reg_OTG_HOST_SINT_STAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x08)))) // 32bit host system int status reg
#define _reg_OTG_HOST_SINT_STEN (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x0C)))) // 32bit host system int enable reg
#define _reg_OTG_HOST_XINT_STAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x18)))) // 32bit host X buf int status reg
#define _reg_OTG_HOST_YINT_STAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x1C)))) // 32bit host Y buf int status reg
#define _reg_OTG_HOST_XYINT_STEN (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x20)))) // 32bit host XY buf int enable reg
#define _reg_OTG_HOST_XFILL_STAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x28)))) // 32bit host X filled status reg
#define _reg_OTG_HOST_YFILL_STAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x2C)))) // 32bit host Y filled status reg
#define _reg_OTG_HOST_ETD_EN (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x40)))) // 32bit host ETD enables reg
#define _reg_OTG_HOST_DIR_ROUTE (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x48)))) // 32bit host direct routing reg
#define _reg_OTG_HOST_IINT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x4C)))) // 32bit host immediate interrupt reg
#define _reg_OTG_HOST_EP_DSTAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x50)))) // 32bit host endpoints done status
#define _reg_OTG_HOST_ETD_DONE (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x54)))) // 32bit host ETD done reg
#define _reg_OTG_HOST_FRM_NUM (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x60)))) // 32bit host frame number reg
#define _reg_OTG_HOST_LSP_THRESH (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x64)))) // 32bit host low speed threshold reg
#define _reg_OTG_HOST_HUB_DESCA (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x68)))) // 32bit host root hub descriptor A
#define _reg_OTG_HOST_HUB_DESCB (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x6C)))) // 32bit host root hub descriptor B
#define _reg_OTG_HOST_HUB_STAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x70)))) // 32bit host root hub status reg
#define _reg_OTG_HOST_PORT1_STAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x74)))) // 32bit host port 1 status bits
#define _reg_OTG_HOST_PORT2_STAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x78)))) // 32bit host port 2 status bits
#define _reg_OTG_HOST_PORT3_STAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_HOST_BASE+0x7c)))) // 32bit host port 3 status bits
#define _reg_OTG_DMA_REV_NUM (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x000)))) // 32bit dma revision number reg
#define _reg_OTG_DMA_DINT_STAT (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x004)))) // 32bit dma int status reg
#define _reg_OTG_DMA_DINT_STEN (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x008)))) // 32bit dma int enable reg
#define _reg_OTG_DMA_ETD_ERR (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x00C)))) // 32bit dma ETD error status reg
#define _reg_OTG_DMA_EP_ERR (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x010)))) // 32bit dma EP error status reg
#define _reg_OTG_DMA_ETD_EN (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x020)))) // 32bit dma ETD DMA enable reg
#define _reg_OTG_DMA_EP_EN (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x024)))) // 32bit dma EP DMA enable reg
#define _reg_OTG_DMA_ETD_ENXREQ (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x028)))) // 32bit dma ETD DMA enable Xtrig req
#define _reg_OTG_DMA_EP_ENXREQ (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x02C)))) // 32bit dma EP DMA enable Ytrig req
#define _reg_OTG_DMA_ETD_ENXYREQ (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x030)))) // 32bit dma ETD DMA enble XYtrig req
#define _reg_OTG_DMA_EP_ENXYREQ (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x034)))) // 32bit dma EP DMA enable XYtrig req
#define _reg_OTG_DMA_ETD_BURST4 (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x038)))) // 32bit dma ETD DMA enble burst4 reg
#define _reg_OTG_DMA_EP_BURST4 (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x03C)))) // 32bit dma EP DMA enable burst4 reg
#define _reg_OTG_DMA_MISC_CTRL (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x040)))) // 32bit dma EP misc control reg
#define _reg_OTG_DMA_ETD_CH_CLR (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x048)))) // 32bit dma ETD clear channel reg
#define _reg_OTG_DMA_EP_CH_CLR (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x04C)))) // 32bit dma EP clear channel reg
#define _reg_OTG_DMA_ETD_MSA(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x100+x*4)))) // 32bit dma ETD mem start addr reg
#define _reg_OTG_DMA_EP_O_MSA(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x180+x*8)))) // 32bit dma EP0 o/p mem start addr
#define _reg_OTG_DMA_EP_I_MSA(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x184+x*8)))) // 32bit dma EP0 i/p mem start addr
#define _reg_OTG_DMA_ETD_BPTR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x200+x*4)))) // 32bit dma ETD0 buf tx pointer reg
#define _reg_OTG_DMA_EP_O_BPTR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x280+8*x)))) // 32bit dma EP0 o/p buf tx pointer
#define _reg_OTG_DMA_EP_I_BPTR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_DMA_BASE+0x284+8*x)))) // 32bit dma EP0 i/p buf tx pointer
#define _reg_OTG_I2C_VENDOR_ID_REG0 (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x00)))) // 8bit I2C reg
#define _reg_OTG_I2C_VENDOR_ID_REG1 (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x01)))) // 8bit I2C reg
#define _reg_OTG_I2C_PRODUCT_ID_REG0 (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x02)))) // 8bit I2C reg
#define _reg_OTG_I2C_PRODUCT_ID_REG1 (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x03)))) // 8bit I2C reg
#define _reg_OTG_I2C_MODE_REG1_SET (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x04)))) // 8bit I2C reg
#define _reg_OTG_I2C_MODE_REG1_CLR (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x05)))) // 8bit I2C reg
#define _reg_OTG_I2C_OTG_CTRL_REG1_SET (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x06)))) // 8bit I2C reg
#define _reg_OTG_I2C_OTG_CTRL_REG1_CLR (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x07)))) // 8bit I2C reg
#define _reg_OTG_I2C_INT_SRC_REG (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x08)))) // 8bit I2C reg
#define _reg_OTG_I2C_INT_LAT_REG_SET (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x0A)))) // 8bit I2C reg
#define _reg_OTG_I2C_INT_LAT_REG_CLR (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x0B)))) // 8bit I2C reg
#define _reg_OTG_I2C_INT_FALSE_REG_SET (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x0C)))) // 8bit I2C reg
#define _reg_OTG_I2C_INT_FALSE_REG_CLR (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x0D)))) // 8bit I2C reg
#define _reg_OTG_I2C_INT_TRUE_REG_SET (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x0E)))) // 8bit I2C reg
#define _reg_OTG_I2C_INT_TRUE_REG_CLR (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x0F)))) // 8bit I2C reg
#define _reg_OTG_I2C_OTG_CTRL_REG2_SET (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x10)))) // 8bit I2C reg
#define _reg_OTG_I2C_OTG_CTRL_REG2_CLR (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x11)))) // 8bit I2C reg
#define _reg_OTG_I2C_MODE_REG2_SET (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x12)))) // 8bit I2C reg
#define _reg_OTG_I2C_MODE_REG2_CLR (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x13)))) // 8bit I2C reg
#define _reg_OTG_I2C_BCD_DEV_REG0 (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x14)))) // 8bit I2C reg
#define _reg_OTG_I2C_BCD_DEV_REG1 (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x15)))) // 8bit I2C reg
#define _reg_OTG_I2C_OTG_XCVR_DEVAD (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x18)))) // 8bit I2C reg
#define _reg_OTG_I2C_SEQ_OP_REG (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x19)))) // 8bit I2C reg
#define _reg_OTG_I2C_SEQ_RD_STARTAD (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x1A)))) // 8bit I2C reg
#define _reg_OTG_I2C_OP_CTRL_REG (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x1B)))) // 8bit I2C reg
#define _reg_OTG_I2C_SCLK_TO_SCL_HPER (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x1E)))) // 8bit I2C reg
#define _reg_OTG_I2C_MASTER_INT_REG (*((volatile unsigned long *)(MX2_IO_ADDRESS(OTG_I2C_BASE+0x1F)))) // 8bit I2C reg
//#########################################
//# EMMA #
//# $1002_6000 to $1002_6FFF #
//#########################################
#define EMMA_BASE_ADDR 0x10026000
#define EMMA_PP_BASE (EMMA_BASE_ADDR+0x000) // base location for post processor
#define EMMA_PRP_BASE (EMMA_BASE_ADDR+0x400) // base location for pre processor
#define EMMA_DEC_BASE (EMMA_BASE_ADDR+0x800) // base location for decoder
#define EMMA_ENC_BASE (EMMA_BASE_ADDR+0xC00) // base location for encoder
#define _reg_EMMA_PP_CNTL (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PP_BASE+0x00)))) // 32bit post processor control reg
#define _reg_EMMA_PP_INTRCTRL (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PP_BASE+0x04)))) // 32bit pp interrupt enable reg
#define _reg_EMMA_PP_INTRSTATUS (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PP_BASE+0x08)))) // 32bit pp interrupt status reg
#define _reg_EMMA_PP_SY_PTR (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PP_BASE+0x0C)))) // 32bit pp source Y data ptr reg
#define _reg_EMMA_PP_SCB_PTR (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PP_BASE+0x10)))) // 32bit pp source CB data ptr reg
#define _reg_EMMA_PP_SCR_PTR (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PP_BASE+0x14)))) // 32bit pp source CR data ptr reg
#define _reg_EMMA_PP_DRGB_PTR (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PP_BASE+0x18)))) // 32bit pp dest RGB data ptr reg
#define _reg_EMMA_PP_QUAN_PTR (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PP_BASE+0x1C)))) // 32bit pp quantizer data ptr reg
#define _reg_EMMA_PP_PROC_PARA (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PP_BASE+0x20)))) // 32bit pp process frame param reg
#define _reg_EMMA_PP_SFRM_WIDTH (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PP_BASE+0x24)))) // 32bit pp source frame width reg
#define _reg_EMMA_PP_DDIS_WIDTH (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PP_BASE+0x28)))) // 32bit pp destinatn display siz reg
#define _reg_EMMA_PP_DIMAGE_SIZE (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PP_BASE+0x2C)))) // 32bit pp destinatn image size reg
#define _reg_EMMA_PP_DPIX_FMT (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PP_BASE+0x30)))) // 32bit pp dest pixel format ctr reg
#define _reg_EMMA_PP_RSIZE_IDX (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PP_BASE+0x34)))) // 32bit pp resize table index reg
#define _reg_EMMA_PP_LOCK_BIT (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PP_BASE+0x38)))) // 32bit pp lock bit reg
#define _reg_EMMA_PP_RSIZE_COEF (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PP_BASE+0x100)))) // 32bit pp resize coef table reg
#define _reg_EMMA_PRP_CNTL (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PRP_BASE+0x00)))) // 32bit preprocessor control reg
#define _reg_EMMA_PRP_INTRCTRL (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PRP_BASE+0x04)))) // 32bit prp interrupt enable reg
#define _reg_EMMA_PRP_INTRSTATUS (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PRP_BASE+0x08)))) // 32bit prp interrupt status reg
#define _reg_EMMA_PRP_SY_PTR (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PRP_BASE+0x0C)))) // 32bit prp source Y data ptr reg
#define _reg_EMMA_PRP_SCB_PTR (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PRP_BASE+0x10)))) // 32bit prp source CB data ptr reg
#define _reg_EMMA_PRP_SCR_PTR (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PRP_BASE+0x14)))) // 32bit prp source CR data ptr reg
#define _reg_EMMA_PRP_DRGB1_PTR (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PRP_BASE+0x18)))) // 32bit prp dest RGB1 data ptr reg
#define _reg_EMMA_PRP_DRGB2_PTR (*((volatile unsigned long *)(MX2_IO_ADDRESS(EMMA_PRP_BASE+0x1C)))) // 32bit prp dest R⌨️ 快捷键说明
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