📄 mx2.h
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#define _reg_CSPI_DMAREG(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(CSPI_BASE_ADDR(x)+0x18)))) // 32bit cspi1 dma ctrl reg
#define _reg_CSPI_RESETREG(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(CSPI_BASE_ADDR(x)+0x1C)))) // 32bit cspi1 soft reset reg
/*SSI1 SSI2*/
#define SSI_BASE_ADDR(x) (0x10010000 + 0x1000*(x-1))
#define _reg_SSI_STX0(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x00)))) // 32bit ssi1 tx reg 0
#define _reg_SSI_STX1(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x04)))) // 32bit ssi1 tx reg 1
#define _reg_SSI_SRX0(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x08)))) // 32bit ssi1 rx reg 0
#define _reg_SSI_SRX1(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x0C)))) // 32bit ssi1 rx reg 1
#define _reg_SSI_SCR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x10)))) // 32bit ssi1 control reg
#define _reg_SSI_SISR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x14)))) // 32bit ssi1 intr status reg
#define _reg_SSI_SIER(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x18)))) // 32bit ssi1 intr enable reg
#define _reg_SSI_STCR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x1C)))) // 32bit ssi1 tx config reg
#define _reg_SSI_SRCR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x20)))) // 32bit ssi1 rx config reg
#define _reg_SSI_STCCR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x24)))) // 32bit ssi1 tx clock control reg
#define _reg_SSI_SRCCR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x28)))) // 32bit ssi1 rx clock control reg
#define _reg_SSI_SFCSR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x2C)))) // 32bit ssi1 fifo control/status reg
#define _reg_SSI_STR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x30)))) // 32bit ssi1 test reg
#define _reg_SSI_SOR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x34)))) // 32bit ssi1 option reg
#define _reg_SSI_SACNT(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x38)))) // 32bit ssi1 ac97 control reg
#define _reg_SSI_SACADD(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x3C)))) // 32bit ssi1 ac97 cmd addr reg
#define _reg_SSI_SACDAT(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x40)))) // 32bit ssi1 ac97 cmd data reg
#define _reg_SSI_SATAG(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x44)))) // 32bit ssi1 ac97 tag reg
#define _reg_SSI_STMSK(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x48)))) // 32bit ssi1 tx time slot mask reg
#define _reg_SSI_SRMSK(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SSI_BASE_ADDR(x)+0x4C)))) // 32bit ssi1 rx time slot mask reg
//#########################################
//# I2C #
//# $1001_2000 to $1001_2FFF #
//#########################################
#define I2C_BASE_ADDR 0x10012000
#define _reg_I2C_IADR (*((volatile unsigned long *)(MX2_IO_ADDRESS(I2C_BASE_ADDR+0x00)))) // 16bit i2c address reg
#define _reg_I2C_IFDR (*((volatile unsigned long *)(MX2_IO_ADDRESS(I2C_BASE_ADDR+0x04)))) // 16bit i2c frequency divider reg
#define _reg_I2C_I2CR (*((volatile unsigned long *)(MX2_IO_ADDRESS(I2C_BASE_ADDR+0x08)))) // 16bit i2c control reg
#define _reg_I2C_I2SR (*((volatile unsigned long *)(MX2_IO_ADDRESS(I2C_BASE_ADDR+0x0C)))) // 16bit i2c status reg
#define _reg_I2C_I2DR (*((volatile unsigned long *)(MX2_IO_ADDRESS(I2C_BASE_ADDR+0x10)))) // 16bit i2c data i/o reg
#define SDHC_BASE_ADDR(x) (0x10013000+0x1000*(x-1))
#define _reg_SDHC_STR_STP_CLK(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SDHC_BASE_ADDR(x)+0x00)))) // 32bit sdhc1 control reg
#define _reg_SDHC_STATUS(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SDHC_BASE_ADDR(x)+0x04)))) // 32bit sdhc1 status reg
#define _reg_SDHC_CLK_RATE(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SDHC_BASE_ADDR(x)+0x08)))) // 32bit sdhc1 clock rate reg
#define _reg_SDHC_CMD_DAT_CONT(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SDHC_BASE_ADDR(x)+0x0C)))) // 32bit sdhc1 cmd/data control reg
#define _reg_SDHC_RESPONSE_TO(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SDHC_BASE_ADDR(x)+0x10)))) // 32bit sdhc1 response time out reg
#define _reg_SDHC_READ_TO(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SDHC_BASE_ADDR(x)+0x14)))) // 32bit sdhc1 read time out reg
#define _reg_SDHC_BLK_LEN(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SDHC_BASE_ADDR(x)+0x18)))) // 32bit sdhc1 block length reg
#define _reg_SDHC_NOB(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SDHC_BASE_ADDR(x)+0x1C)))) // 32bit sdhc1 number of blocks reg
#define _reg_SDHC_REV_NO(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SDHC_BASE_ADDR(x)+0x20)))) // 32bit sdhc1 revision number reg
#define _reg_SDHC_INT_MASK(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SDHC_BASE_ADDR(x)+0x24)))) // 32bit sdhc1 interrupt mask reg
#define _reg_SDHC_CMD(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SDHC_BASE_ADDR(x)+0x28)))) // 32bit sdhc1 command code reg
#define _reg_SDHC_ARGH(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SDHC_BASE_ADDR(x)+0x2C)))) // 32bit sdhc1 argument high reg
#define _reg_SDHC_ARGL(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SDHC_BASE_ADDR(x)+0x30)))) // 32bit sdhc1 argument low reg
#define _reg_SDHC_RES_FIFO(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SDHC_BASE_ADDR(x)+0x34)))) // 32bit sdhc1 response fifo reg
#define _reg_SDHC_BUFFER_ACCESS(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(SDHC_BASE_ADDR(x)+0x38)))) // 32bit sdhc1 buffer access reg
//#########################################
//# GPIO #
//# $1001_5000 to $1001_5FFF #
//#########################################
#define GPIOA 0
#define GPIOB 1
#define GPIOC 2
#define GPIOD 3
#define GPIOE 4
#define GPIOF 5
/* Use as GPIO_BASE_ADDR(GPIOA)- GPIO_BASE_ADDR(GPIOF)*/
#define GPIO_BASE_ADDR(x) (0x10015000+x*0x100)
#define _reg_GPIO_DDIR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPIO_BASE_ADDR(x)+0x00)))) // 32bit gpio pta data direction reg
#define _reg_GPIO_OCR1(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPIO_BASE_ADDR(x)+0x04)))) // 32bit gpio pta output config 1 reg
#define _reg_GPIO_OCR2(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPIO_BASE_ADDR(x)+0x08)))) // 32bit gpio pta output config 2 reg
#define _reg_GPIO_ICONFA1(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPIO_BASE_ADDR(x)+0x0C)))) // 32bit gpio pta input config A1 reg
#define _reg_GPIO_ICONFA2(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPIO_BASE_ADDR(x)+0x10)))) // 32bit gpio pta input config A2 reg
#define _reg_GPIO_ICONFB1(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPIO_BASE_ADDR(x)+0x14)))) // 32bit gpio pta input config B1 reg
#define _reg_GPIO_ICONFB2(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPIO_BASE_ADDR(x)+0x18)))) // 32bit gpio pta input config B2 reg
#define _reg_GPIO_DR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPIO_BASE_ADDR(x)+0x1C)))) // 32bit gpio pta data reg
#define _reg_GPIO_GIUS(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPIO_BASE_ADDR(x)+0x20)))) // 32bit gpio pta in use reg
#define _reg_GPIO_SSR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPIO_BASE_ADDR(x)+0x24)))) // 32bit gpio pta sample status reg
#define _reg_GPIO_ICR1(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPIO_BASE_ADDR(x)+0x28)))) // 32bit gpio pta interrupt ctrl 1 reg
#define _reg_GPIO_ICR2(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPIO_BASE_ADDR(x)+0x2C)))) // 32bit gpio pta interrupt ctrl 2 reg
#define _reg_GPIO_IMR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPIO_BASE_ADDR(x)+0x30)))) // 32bit gpio pta interrupt mask reg
#define _reg_GPIO_ISR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPIO_BASE_ADDR(x)+0x34)))) // 32bit gpio pta interrupt status reg
#define _reg_GPIO_GPR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPIO_BASE_ADDR(x)+0x38)))) // 32bit gpio pta general purpose reg
#define _reg_GPIO_SWR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPIO_BASE_ADDR(x)+0x3C)))) // 32bit gpio pta software reset reg
#define _reg_GPIO_PUEN(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPIO_BASE_ADDR(x)+0x40)))) // 32bit gpio pta pull up enable reg
#define GPIO_REG_BASE 0x10015600
#define _reg_GPIO_PMASK (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPIO_REG_BASE+0x00)))) // 32bit gpio interrupt mask reg
//#########################################
//# AUDMUX #
//# $1001_6000 to $1001_6FFF #
//#########################################
#define AUDMUX_BASE_ADDR 0x10016000
#define _reg_AUDMUX_HPCR1 (*((volatile unsigned long *)(MX2_IO_ADDRESS(AUDMUX_BASE_ADDR+0x00)))) // 32bit audmux host config reg 1
#define _reg_AUDMUX_HPCR2 (*((volatile unsigned long *)(MX2_IO_ADDRESS(AUDMUX_BASE_ADDR+0x04)))) // 32bit audmux host config reg 2
#define _reg_AUDMUX_HPCR3 (*((volatile unsigned long *)(MX2_IO_ADDRESS(AUDMUX_BASE_ADDR+0x08)))) // 32bit audmux host config reg 3
#define _reg_AUDMUX_PPCR1 (*((volatile unsigned long *)(MX2_IO_ADDRESS(AUDMUX_BASE_ADDR+0x10)))) // 32bit audmux pripheral config 1
#define _reg_AUDMUX_PPCR2 (*((volatile unsigned long *)(MX2_IO_ADDRESS(AUDMUX_BASE_ADDR+0x14)))) // 32bit audmux pripheral config 2
#define _reg_AUDMUX_PPCR3 (*((volatile unsigned long *)(MX2_IO_ADDRESS(AUDMUX_BASE_ADDR+0x1C)))) // 32bit audmux pripheral config 3
//#########################################
//# AIPI2 #
//# $1002_0000 to $1002_0FFF #
//#########################################
#define AIPI2_BASE_ADDR 0x10020000
#define _reg_AIPI2_PSR0 (*((volatile unsigned long *)(MX2_IO_ADDRESS(AIPI2_BASE_ADDR+0x00)))) // 32bit Peripheral Size Reg 0
#define _reg_AIPI2_PSR1 (*((volatile unsigned long *)(MX2_IO_ADDRESS(AIPI2_BASE_ADDR+0x04)))) // 32bit Peripheral Size Reg 1
#define _reg_AIPI2_PAR (*((volatile unsigned long *)(MX2_IO_ADDRESS(AIPI2_BASE_ADDR+0x08)))) // 32bit Peripheral Access Reg
//#########################################
//# LCDC #
//# $1002_1000 to $1002_1FFF #
//#########################################
#define LCDC_BASE_ADDR 0x10021000
#define _reg_LCDC_LSSAR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x00)))) // 32bit lcdc screen start addr reg
#define _reg_LCDC_LSR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x04)))) // 32bit lcdc size reg
#define _reg_LCDC_LVPWR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x08)))) // 32bit lcdc virtual page width reg
#define _reg_LCDC_LCPR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x0C)))) // 32bit lcd cursor position reg
#define _reg_LCDC_LCWHBR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x10)))) // 32bit lcd cursor width/heigh/blink
#define _reg_LCDC_LCCMR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x14)))) // 32bit lcd color cursor mapping reg
#define _reg_LCDC_LPCR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x18)))) // 32bit lcdc panel config reg
#define _reg_LCDC_LHCR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x1C)))) // 32bit lcdc horizontal config reg
#define _reg_LCDC_LVCR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x20)))) // 32bit lcdc vertical config reg
#define _reg_LCDC_LPOR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x24)))) // 32bit lcdc panning offset reg
#define _reg_LCDC_LSCR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x28)))) // 32bit lcdc sharp config 1 reg
#define _reg_LCDC_LPCCR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x2C)))) // 32bit lcdc pwm contrast ctrl reg
#define _reg_LCDC_LDCR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x30)))) // 32bit lcdc dma control reg
#define _reg_LCDC_LRMCR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x34)))) // 32bit lcdc refresh mode ctrl reg
#define _reg_LCDC_LICR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x38)))) // 32bit lcdc interrupt config reg
#define _reg_LCDC_LIER (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x3C)))) // 32bit lcdc interrupt enable reg
#define _reg_LCDC_LISR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x40)))) // 32bit lcdc interrupt status reg
#define _reg_LCDC_LGWSAR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x50)))) // 32bit lcdc graphic win start add
#define _reg_LCDC_LGWSR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x54)))) // 32bit lcdc graphic win size reg
#define _reg_LCDC_LGWVPWR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x58)))) // 32bit lcdc graphic win virtual pg
#define _reg_LCDC_LGWPOR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x5C)))) // 32bit lcdc graphic win pan offset
#define _reg_LCDC_LGWPR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x60)))) // 32bit lcdc graphic win positon reg
#define _reg_LCDC_LGWCR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x64)))) // 32bit lcdc graphic win control reg
#define _reg_LCDC_LGWDCR (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x68)))) // 32bit lcdc graphic win DMA control reg
#define _reg_LCDC_BPLUT_BASE(regno) (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0x800+4*(regno))))) // Background Plane LUT (800 - BFC)
#define _reg_LCDC_GWLUT_BASE(regno) (*((volatile unsigned long *)(MX2_IO_ADDRESS(LCDC_BASE_ADDR+0xC00+4*(regno))))) // Background Plane LUT (C00 - FFC)
//#########################################
//# SLCDC #
//# $1002_2000 to $1002_2FFF #
//#########################################
#define SLCDC_BASE_ADDR 0x10022000
#define _reg_SLCDC_DBADDR (*((volatile unsigned long *)(MX2_IO_ADDRESS(SLCDC_BASE_ADDR+0x00)))) // 32bit slcdc data base addr
#define _reg_SLCDC_DBUF_SIZE (*((volatile unsigned long *)(MX2_IO_ADDRESS(SLCDC_BASE_ADDR+0x04)))) // 32bit slcdc data buffer size high
#define _reg_SLCDC_CBADDR (*((volatile unsigned long *)(MX2_IO_ADDRESS(SLCDC_BASE_ADDR+0x08)))) // 32bit slcdc cmd base addr high
#define _reg_SLCDC_CBUF_SIZE (*((volatile unsigned long *)(MX2_IO_ADDRESS(SLCDC_BASE_ADDR+0x0C)))) // 32bit slcdc cmd buffer size high
#define _reg_SLCDC_CBUF_SSIZE (*((volatile unsigned long *)(MX2_IO_ADDRESS(SLCDC_BASE_ADDR+0x10)))) // 32bit slcdc cmd string size
#define _reg_SLCDC_FIFO_CONFIG (*((volatile unsigned long *)(MX2_IO_ADDRESS(SLCDC_BASE_ADDR+0x14)))) // 32bit slcdc fifo config reg
#define _reg_SLCDC_LCD_CONFIG (*((volatile unsigned long *)(MX2_IO_ADDRESS(SLCDC_BASE_ADDR+0x18)))) // 32bit slcdc lcd controller config
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