📄 mx2.h
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//# $1000_0000 to $1000_0FFF #
//#########################################
#define AIPI1_BASE_ADDR 0x10000000
#define _reg_AIPI1_PSR0 (*((volatile unsigned long *)(MX2_IO_ADDRESS(AIPI1_BASE_ADDR+0x00)))) // 32bit Peripheral Size Reg 0
#define _reg_AIPI1_PSR1 (*((volatile unsigned long *)(MX2_IO_ADDRESS(AIPI1_BASE_ADDR+0x04)))) // 32bit Peripheral Size Reg 1
#define _reg_AIPI1_PAR (*((volatile unsigned long *)(MX2_IO_ADDRESS(AIPI1_BASE_ADDR+0x08)))) // 32bit Peripheral Access Reg
//#########################################
//# DMA #
//# $1000_1000 to $1000_1FFF #
//#########################################
#define DMA_BASE_ADDR 0x10001000
#define DMA_SYS_BASE DMA_BASE_ADDR // base location for system
#define DMA_M2D_BASE (DMA_BASE_ADDR+0x040) // base location for 2D memory reg
#define DMA_CH_BASE(x) (DMA_BASE_ADDR+0x080+0x040*(x))
#define DMA_TEST_BASE (DMA_BASE_ADDR+0x480) // base location for test registers
#define _reg_DMA_DCR (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_SYS_BASE)))) // 32bit dma control reg
#define _reg_DMA_DISR (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_SYS_BASE+0x004)))) // 32bit dma interrupt status reg
#define _reg_DMA_DIMR (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_SYS_BASE+0x008)))) // 32bit dma interrupt mask reg
#define _reg_DMA_DBTOSR (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_SYS_BASE+0x00C)))) // 32bit dma burst timeout stat reg
#define _reg_DMA_DRTOSR (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_SYS_BASE+0x010)))) // 32bit dma req timeout status reg
#define _reg_DMA_DSESR (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_SYS_BASE+0x014)))) // 32bit dma transfer err status reg
#define _reg_DMA_DBOSR (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_SYS_BASE+0x018)))) // 32bit dma buffer overflow stat reg
#define _reg_DMA_DBTOCR (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_SYS_BASE+0x01C)))) // 32bit dma burst timeout ctrl reg
#define _reg_DMA_WSRA (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_M2D_BASE+0x000)))) // 32bit dma W-size A reg
#define _reg_DMA_XSRA (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_M2D_BASE+0x004)))) // 32bit dma X-size A reg
#define _reg_DMA_YSRA (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_M2D_BASE+0x008)))) // 32bit dma Y-size A reg
#define _reg_DMA_WSRB (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_M2D_BASE+0x00C)))) // 32bit dma W-size B reg
#define _reg_DMA_XSRB (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_M2D_BASE+0x010)))) // 32bit dma X-size B reg
#define _reg_DMA_YSRB (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_M2D_BASE+0x014)))) // 32bit dma Y-size B reg
#define _reg_DMA_SAR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_CH_BASE(x)))))
#define _reg_DMA_DAR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_CH_BASE(x)+0x004))))
#define _reg_DMA_CNTR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_CH_BASE(x)+0x008))))
#define _reg_DMA_CCR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_CH_BASE(x)+0x00C)))) // 32bit dma ch0 control reg
#define _reg_DMA_RSSR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_CH_BASE(x)+0x010)))) // 32bit dma ch0 req source sel reg
#define _reg_DMA_BLR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_CH_BASE(x)+0x014)))) // 32bit dma ch0 burst lenght reg
#define _reg_DMA_RTOR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_CH_BASE(x)+0x018)))) // 32bit dma ch0 req time out reg
#define _reg_DMA_BUCR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_CH_BASE(x)+0x018)))) // 32bit dma ch0 bus utilization reg
#define _reg_DMA_CCNR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_CH_BASE(x)+0x01C)))) // 32bit dma ch0
#define _reg_DMA_TCR (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_TEST_BASE+0x000)))) // 32bit dma test control reg
#define _reg_DMA_TFIFOAR (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_TEST_BASE+0x004)))) // 32bit dma test fifo A reg
#define _reg_DMA_TDRR (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_TEST_BASE+0x008)))) // 32bit dma test request reg
#define _reg_DMA_TDIPR (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_TEST_BASE+0x00C)))) // 32bit dma test in progress reg
#define _reg_DMA_TFIFOBR (*((volatile unsigned long *)(MX2_IO_ADDRESS(DMA_TEST_BASE+0x010)))) // 32bit dma test fifo B reg
//#########################################
//# WDOG #
//# $1000_2000 to $1000_2FFF #
//#########################################
#define GPT1 0
#define GPT2 1
#define GPT3 2
#define WDOG_BASE_ADDR 0x10002000
#define _reg_WDOG_WCR (*((volatile unsigned short *)(MX2_IO_ADDRESS(WDOG_BASE_ADDR+0x00)))) // 16bit watchdog control reg
#define _reg_WDOG_WSR (*((volatile unsigned short *)(MX2_IO_ADDRESS(WDOG_BASE_ADDR+0x02)))) // 16bit watchdog service reg
#define _reg_WDOG_WRSR (*((volatile unsigned short *)(MX2_IO_ADDRESS(WDOG_BASE_ADDR+0x04)))) // 16bit watchdog reset status reg
#define _reg_WDOG_WPR (*((volatile unsigned short *)(MX2_IO_ADDRESS(WDOG_BASE_ADDR+0x06)))) // 16bit watchdog protect reg
#define GPT_BASE_ADDR(x) (0x10003000+0x1000*x)
#define _reg_GPT_TCTL(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPT_BASE_ADDR(x)+0x00)))) // 32bit timer control reg
#define _reg_GPT_TPRER(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPT_BASE_ADDR(x)+0x04)))) // 32bit timer prescaler reg
#define _reg_GPT_TCMP(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPT_BASE_ADDR(x)+0x08)))) // 32bit timer compare reg
#define _reg_GPT_TCR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPT_BASE_ADDR(x)+0x0C)))) // 32bit timer capture reg
#define _reg_GPT_TCN(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPT_BASE_ADDR(x)+0x10)))) // 32bit timer counter reg
#define _reg_GPT_TSTAT(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(GPT_BASE_ADDR(x)+0x14)))) // 32bit timer status reg
//#########################################
//# PWM #
//# $1000_6000 to $1000_6FFF #
//#########################################
#define PWM_BASE_ADDR 0x10006000
#define _reg_PWM_PWMC (*((volatile unsigned long *)(MX2_IO_ADDRESS(PWM_BASE_ADDR+0x00)))) // 32bit pwm control reg
#define _reg_PWM_PWMS (*((volatile unsigned long *)(MX2_IO_ADDRESS(PWM_BASE_ADDR+0x04)))) // 32bit pwm sample reg
#define _reg_PWM_PWMP (*((volatile unsigned long *)(MX2_IO_ADDRESS(PWM_BASE_ADDR+0x08)))) // 32bit pwm period reg
#define _reg_PWM_PWMCNT (*((volatile unsigned long *)(MX2_IO_ADDRESS(PWM_BASE_ADDR+0x0C)))) // 32bit pwm counter reg
#define _reg_PWM_PWMTEST1 (*((volatile unsigned long *)(MX2_IO_ADDRESS(PWM_BASE_ADDR+0x10)))) // 32bit pwm test reg
//#########################################
//# RTC #
//# $1000_7000 to $1000_7FFF #
//#########################################
#define RTC_BASE_ADDR 0x10007000
#define _reg_RTC_HOURMIN (*((volatile unsigned long *)(MX2_IO_ADDRESS(RTC_BASE_ADDR+0x00)))) // 32bit rtc hour/min counter reg
#define _reg_RTC_SECOND (*((volatile unsigned long *)(MX2_IO_ADDRESS(RTC_BASE_ADDR+0x04)))) // 32bit rtc seconds counter reg
#define _reg_RTC_ALRM_HM (*((volatile unsigned long *)(MX2_IO_ADDRESS(RTC_BASE_ADDR+0x08)))) // 32bit rtc alarm hour/min reg
#define _reg_RTC_ALRM_SEC (*((volatile unsigned long *)(MX2_IO_ADDRESS(RTC_BASE_ADDR+0x0C)))) // 32bit rtc alarm seconds reg
#define _reg_RTC_RTCCTL (*((volatile unsigned long *)(MX2_IO_ADDRESS(RTC_BASE_ADDR+0x10)))) // 32bit rtc control reg
#define _reg_RTC_RTCISR (*((volatile unsigned long *)(MX2_IO_ADDRESS(RTC_BASE_ADDR+0x14)))) // 32bit rtc interrupt status reg
#define _reg_RTC_RTCIENR (*((volatile unsigned long *)(MX2_IO_ADDRESS(RTC_BASE_ADDR+0x18)))) // 32bit rtc interrupt enable reg
#define _reg_RTC_STPWCH (*((volatile unsigned long *)(MX2_IO_ADDRESS(RTC_BASE_ADDR+0x1C)))) // 32bit rtc stopwatch min reg
#define _reg_RTC_DAYR (*((volatile unsigned long *)(MX2_IO_ADDRESS(RTC_BASE_ADDR+0x20)))) // 32bit rtc days counter reg
#define _reg_RTC_DAYALARM (*((volatile unsigned long *)(MX2_IO_ADDRESS(RTC_BASE_ADDR+0x24)))) // 32bit rtc day alarm reg
#define _reg_RTC_TEST1 (*((volatile unsigned long *)(MX2_IO_ADDRESS(RTC_BASE_ADDR+0x28)))) // 32bit rtc test reg 1
#define _reg_RTC_TEST2 (*((volatile unsigned long *)(MX2_IO_ADDRESS(RTC_BASE_ADDR+0x2C)))) // 32bit rtc test reg 2
#define _reg_RTC_TEST3 (*((volatile unsigned long *)(MX2_IO_ADDRESS(RTC_BASE_ADDR+0x30)))) // 32bit rtc test reg 3
//#########################################
//# KPP #
//# $1000_8000 to $1000_8FFF #
//#########################################
#define KPP_BASE_ADDR 0x10008000
#define _reg_KPP_KPCR (*((volatile unsigned long *)(MX2_IO_ADDRESS(KPP_BASE_ADDR+0x00)))) // 16bit kpp keypad control reg
#define _reg_KPP_KPSR (*((volatile unsigned long *)(MX2_IO_ADDRESS(KPP_BASE_ADDR+0x02)))) // 16bit kpp keypad status reg
#define _reg_KPP_KDDR (*((volatile unsigned long *)(MX2_IO_ADDRESS(KPP_BASE_ADDR+0x04)))) // 16bit kpp keypad data directon reg
#define _reg_KPP_KPDR (*((volatile unsigned long *)(MX2_IO_ADDRESS(KPP_BASE_ADDR+0x06)))) // 16bit kpp keypad data reg
//#########################################
//# OWIRE #
//# $1000_9000 to $1000_9FFF #
//#########################################
#define OWIRE_BASE_ADDR 0x10009000
#define _reg_OWIRE_CTRL (*((volatile unsigned long *)(MX2_IO_ADDRESS(OWIRE_BASE_ADDR+0x00)))) // 16bit owire control reg
#define _reg_OWIRE_TIME_DIV (*((volatile unsigned long *)(MX2_IO_ADDRESS(OWIRE_BASE_ADDR+0x02)))) // 16bit owire time divider reg
#define _reg_OWIRE_RESET (*((volatile unsigned long *)(MX2_IO_ADDRESS(OWIRE_BASE_ADDR+0x04)))) // 16bit owire reset reg
#define UART_1 0
#define UART_2 1
#define UART_3 2
#define UART_4 3
/* UART1-UART4*/
#define UART_BASE_ADDR(x) 0x1000A000+0x1000*(x)
#define _reg_UART_URXD(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(UART_BASE_ADDR(x)+0x00)))) // 32bit uart1 receiver reg
#define _reg_UART_UTXD(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(UART_BASE_ADDR(x)+0x40)))) // 32bit uart1 transmitter reg
#define _reg_UART_UCR1(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(UART_BASE_ADDR(x)+0x80)))) // 32bit uart1 control 1 reg
#define _reg_UART_UCR2(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(UART_BASE_ADDR(x)+0x84)))) // 32bit uart1 control 2 reg
#define _reg_UART_UCR3(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(UART_BASE_ADDR(x)+0x88)))) // 32bit uart1 control 3 reg
#define _reg_UART_UCR4(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(UART_BASE_ADDR(x)+0x8C)))) // 32bit uart1 control 4 reg
#define _reg_UART_UFCR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(UART_BASE_ADDR(x)+0x90)))) // 32bit uart1 fifo control reg
#define _reg_UART_USR1(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(UART_BASE_ADDR(x)+0x94)))) // 32bit uart1 status 1 reg
#define _reg_UART_USR2(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(UART_BASE_ADDR(x)+0x98)))) // 32bit uart1 status 2 reg
#define _reg_UART_UESC(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(UART_BASE_ADDR(x)+0x9C)))) // 32bit uart1 escape char reg
#define _reg_UART_UTIM(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(UART_BASE_ADDR(x)+0xA0)))) // 32bit uart1 escape timer reg
#define _reg_UART_UBIR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(UART_BASE_ADDR(x)+0xA4)))) // 32bit uart1 BRM incremental reg
#define _reg_UART_UBMR(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(UART_BASE_ADDR(x)+0xA8)))) // 32bit uart1 BRM modulator reg
#define _reg_UART_UBRC(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(UART_BASE_ADDR(x)+0xAC)))) // 32bit uart1 baud rate count reg
#define _reg_UART_ONEMS(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(UART_BASE_ADDR(x)+0xB0)))) // 32bit uart1 one ms reg
#define _reg_UART_UTS(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(UART_BASE_ADDR(x)+0xB4)))) // 32bit uart1 test reg
//#########################################
//# CSPI1-2 #
//# #
//#########################################
#define CSPI_BASE_ADDR(x) (0x1000E000+0x1000*(x-1))
#define _reg_CSPI_RXDATAREG(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(CSPI_BASE_ADDR(x)+0x00)))) // 32bit cspi1 receive data reg
#define _reg_CSPI_TXDATAREG(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(CSPI_BASE_ADDR(x)+0x04)))) // 32bit cspi1 transmit data reg
#define _reg_CSPI_CONTROLREG(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(CSPI_BASE_ADDR(x)+0x08)))) // 32bit cspi1 control reg
#define _reg_CSPI_INTREG(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(CSPI_BASE_ADDR(x)+0x0C)))) // 32bit cspi1 interrupt stat/ctr reg
#define _reg_CSPI_TESTREG(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(CSPI_BASE_ADDR(x)+0x10)))) // 32bit cspi1 test reg
#define _reg_CSPI_PERIODREG(x) (*((volatile unsigned long *)(MX2_IO_ADDRESS(CSPI_BASE_ADDR(x)+0x14)))) // 32bit cspi1 sample period ctrl reg
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