📄 light.lst
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00A1: 57 58 MOV X,88 (0279) mov X, <__pXIData ; pointer to the xidata area.
00A3: 08 PUSH A (0280) push A
00A4: 28 ROMX (0281) romx ; get the MSB of xidata's address
00A5: 53 1B MOV [__r0],A (0282) mov [__r0], A
00A7: 18 POP A (0283) pop A
00A8: 75 INC X (0284) inc X
00A9: 09 00 ADC A,0 (0285) adc A, 0
00AB: 28 ROMX (0286) romx ; get the LSB of xidata's address
00AC: 4B SWAP A,X (0287) swap A, X
00AD: 51 1B MOV A,[27] (0288) mov A, [__r0] ; pXIData (in [A,X]) points to the
(0289) ; XIData structure list in flash
00AF: 80 04 JMP 0x00B4 (0290) jmp .AccessStruct
(0291)
(0292) ; Unpack one element in the xidata "structure list" that specifies the
(0293) ; values of C variables. Each structure contains 3 member elements.
(0294) ; The first is a pointer to a contiguous block of RAM to be initial-
(0295) ; ized. Blocks are always 255 bytes or less in length and never cross
(0296) ; RAM page boundaries. The list terminates when the MSB of the pointer
(0297) ; contains 0xFF. There are two formats for the struct depending on the
(0298) ; value in the second member element, an unsigned byte:
(0299) ; (1) If the value of the second element is non-zero, it represents
(0300) ; the 'size' of the block of RAM to be initialized. In this case, the
(0301) ; third member of the struct is an array of bytes of length 'size' and
(0302) ; the bytes are copied to the block of RAM.
(0303) ; (2) If the value of the second element is zero, the block of RAM is
(0304) ; to be cleared to zero. In this case, the third member of the struct
(0305) ; is an unsigned byte containing the number of bytes to clear.
(0306)
(0307) .AccessNextStructLoop:
00B1: 75 INC X (0308) inc X ; pXIData++
00B2: 09 00 ADC A,0 (0309) adc A, 0
(0310) .AccessStruct: ; Entry point for first block
(0311) ;
(0312) ; Assert: pXIData in [A,X] points to the beginning of an XIData struct.
(0313) ;
00B4: 62 E3 00 MOV REG[227],0 (0314) M8C_ClearWDT ; Clear the watchdog for long inits
00B7: 08 PUSH A (0315) push A
00B8: 28 ROMX (0316) romx ; MSB of RAM addr (CPU.A <- *pXIData)
00B9: 60 D5 MOV REG[213],A (0317) mov reg[MVW_PP], A ; for use with MVI write operations
00BB: 74 INC A (0318) inc A ; End of Struct List? (MSB==0xFF?)
00BC: A0 4B JZ 0x0108 (0319) jz .C_RTE_WrapUp ; Yes, C runtime environment complete
00BE: 18 POP A (0320) pop A ; restore pXIData to [A,X]
00BF: 75 INC X (0321) inc X ; pXIData++
00C0: 09 00 ADC A,0 (0322) adc A, 0
00C2: 08 PUSH A (0323) push A
00C3: 28 ROMX (0324) romx ; LSB of RAM addr (CPU.A <- *pXIData)
00C4: 53 1B MOV [__r0],A (0325) mov [__r0], A ; RAM Addr now in [reg[MVW_PP],[__r0]]
00C6: 18 POP A (0326) pop A ; restore pXIData to [A,X]
00C7: 75 INC X (0327) inc X ; pXIData++ (point to size)
00C8: 09 00 ADC A,0 (0328) adc A, 0
00CA: 08 PUSH A (0329) push A
00CB: 28 ROMX (0330) romx ; Get the size (CPU.A <- *pXIData)
00CC: A0 1C JZ 0x00E9 (0331) jz .ClearRAMBlockToZero ; If Size==0, then go clear RAM
00CE: 53 1A MOV [__r1],A (0332) mov [__r1], A ; else downcount in __r1
00D0: 18 POP A (0333) pop A ; restore pXIData to [A,X]
(0334)
(0335) .CopyNextByteLoop:
(0336) ; For each byte in the structure's array member, copy from flash to RAM.
(0337) ; Assert: pXIData in [A,X] points to previous byte of flash source;
(0338) ; [reg[MVW_PP],[__r0]] points to next RAM destination;
(0339) ; __r1 holds a non-zero count of the number of bytes remaining.
(0340) ;
00D1: 75 INC X (0341) inc X ; pXIData++ (point to next data byte)
00D2: 09 00 ADC A,0 (0342) adc A, 0
00D4: 08 PUSH A (0343) push A
00D5: 28 ROMX (0344) romx ; Get the data value (CPU.A <- *pXIData)
00D6: 3F 1B MVI [__r0],A (0345) mvi [__r0], A ; Transfer the data to RAM
00D8: 47 1B FF TST [27],255 (0346) tst [__r0], 0xff ; Check for page crossing
00DB: B0 06 JNZ 0x00E2 (0347) jnz .CopyLoopTail ; No crossing, keep going
00DD: 5D D5 MOV A,REG[213] (0348) mov A, reg[ MVW_PP] ; If crossing, bump MVW page reg
00DF: 74 INC A (0349) inc A
00E0: 60 D5 MOV REG[213],A (0350) mov reg[ MVW_PP], A
(0351) .CopyLoopTail:
00E2: 18 POP A (0352) pop A ; restore pXIData to [A,X]
00E3: 7A 1A DEC [__r1] (0353) dec [__r1] ; End of this array in flash?
00E5: BF EB JNZ 0x00D1 (0354) jnz .CopyNextByteLoop ; No, more bytes to copy
00E7: 8F C9 JMP 0x00B1 (0355) jmp .AccessNextStructLoop ; Yes, initialize another RAM block
(0356)
(0357) .ClearRAMBlockToZero:
00E9: 18 POP A (0358) pop A ; restore pXIData to [A,X]
00EA: 75 INC X (0359) inc X ; pXIData++ (point to next data byte)
00EB: 09 00 ADC A,0 (0360) adc A, 0
00ED: 08 PUSH A (0361) push A
00EE: 28 ROMX (0362) romx ; Get the run length (CPU.A <- *pXIData)
00EF: 53 1A MOV [__r1],A (0363) mov [__r1], A ; Initialize downcounter
00F1: 50 00 MOV A,0 (0364) mov A, 0 ; Initialize source data
(0365)
(0366) .ClearRAMBlockLoop:
(0367) ; Assert: [reg[MVW_PP],[__r0]] points to next RAM destination and
(0368) ; __r1 holds a non-zero count of the number of bytes remaining.
(0369) ;
00F3: 3F 1B MVI [__r0],A (0370) mvi [__r0], A ; Clear a byte
00F5: 47 1B FF TST [27],255 (0371) tst [__r0], 0xff ; Check for page crossing
00F8: B0 08 JNZ 0x0101 (0372) jnz .ClearLoopTail ; No crossing, keep going
00FA: 5D D5 MOV A,REG[213] (0373) mov A, reg[ MVW_PP] ; If crossing, bump MVW page reg
00FC: 74 INC A (0374) inc A
00FD: 60 D5 MOV REG[213],A (0375) mov reg[ MVW_PP], A
00FF: 50 00 MOV A,0 (0376) mov A, 0 ; Restore the zero used for clearing
(0377) .ClearLoopTail:
0101: 7A 1A DEC [__r1] (0378) dec [__r1] ; Was this the last byte?
0103: BF EF JNZ 0x00F3 (0379) jnz .ClearRAMBlockLoop ; No, continue
0105: 18 POP A (0380) pop A ; Yes, restore pXIData to [A,X] and
0106: 8F AA JMP 0x00B1 (0381) jmp .AccessNextStructLoop ; initialize another RAM block
(0382)
(0383) .C_RTE_WrapUp:
0108: 18 POP A (0384) pop A ; balance stack
(0385)
(0386) ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
(0387)
(0388) C_RTE_Done:
(0389)
(0390) ENDIF ; C_LANGUAGE_SUPPORT
(0391)
(0392) ;-------------------------------
(0393) ; Voltage Stabilization for SMP
(0394) ;-------------------------------
(0395)
(0396) IF ( POWER_SETTING & POWER_SET_5V0) ; 5.0V Operation
(0397) IF ( SWITCH_MODE_PUMP ^ 1 ) ; SMP is operational
(0398) ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(0399) ; When using the SMP at 5V, we must wait for Vdd to slew from 3.1V to
(0400) ; 5V before enabling the Precision Power-On Reset (PPOR).
(0401) ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(0402) or reg[INT_MSK0],INT_MSK0_SLEEP
(0403) M8C_SetBank1
(0404) and reg[OSC_CR0], ~OSC_CR0_SLEEP
(0405) or reg[OSC_CR0], OSC_CR0_SLEEP_512Hz
(0406) M8C_SetBank0
(0407) M8C_ClearWDTAndSleep ; Restart the sleep timer
(0408) mov reg[INT_VC], 0 ; Clear all pending interrupts
(0409) .WaitFor2ms:
(0410) tst reg[INT_CLR0], INT_MSK0_SLEEP ; Test the SleepTimer Interrupt Status
(0411) jz .WaitFor2ms ; Branch fails when 2 msec has passed
(0412) ENDIF ; SMP is operational
(0413) ENDIF ; 5.0V Operation
(0414)
(0415) ;-------------------------------
(0416) ; Set Power-On Reset (POR) Level
(0417) ;-------------------------------
0109: 71 10 OR F,16 (0418) M8C_SetBank1
(0419)
(0420) IF (POWER_SETTING & POWER_SET_2V7) ; 2.7V Operation?
(0421) ; Yes, lowest trip already set
(0422) ELSE ; No, must adjust POR...
(0423) IF (POWER_SETTING & POWER_SET_3V3) ; 3.3V Operation?
(0424) or reg[VLT_CR], VLT_CR_POR_MID ; Yes, change to midpoint trip
(0425) ELSE
(0426) IF (POWER_SETTING & POWER_SET_5V0) ; 5.0V Operation?
(0427) IF (POWER_SETTING & POWER_SET_SLOW_IMO) ; and Slow Mode?
(0428) or reg[VLT_CR], VLT_CR_POR_MID ; Yes, set to midpoint trip
(0429) ELSE ; No, fast mode
(0430) IF ( CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz ) ; As fast as 24MHz?
010B: 43 E3 10 OR REG[227],16 (0431) or reg[VLT_CR], VLT_CR_POR_MID ; No, change to midpoint trip
(0432) ELSE ; 24HMz ;
(0433) or reg[VLT_CR], VLT_CR_POR_HIGH ; Yes, switch to highest setting
(0434) ENDIF ; 24MHz
(0435) ENDIF ; Slow Mode
(0436) ENDIF ; 5.0V Operation
(0437) ENDIF ; 3.3V Operation
(0438) ENDIF ; 2.7V Operation
(0439)
010E: 70 EF AND F,239 (0440) M8C_SetBank0
(0441)
(0442) ;----------------------------
(0443) ; Wrap up and invoke "main"
(0444) ;----------------------------
(0445)
(0446) ; Disable the Sleep interrupt that was used for timing above. In fact,
(0447) ; no interrupts should be enabled now, so may as well clear the register.
(0448) ;
0110: 62 E0 00 MOV REG[224],0 (0449) mov reg[INT_MSK0],0
(0450)
(0451) ; Everything has started OK. Now select requested CPU & sleep frequency.
(0452) ;
0113: 71 10 OR F,16 (0453) M8C_SetBank1
0115: 62 E0 02 MOV REG[224],2 (0454) mov reg[OSC_CR0],(SLEEP_TIMER_JUST | CPU_CLOCK_JUST)
0118: 70 EF AND F,239 (0455) M8C_SetBank0
(0456)
(0457) ; Global Interrupt are NOT enabled, this should be done in main().
(0458) ; LVD is set but will not occur unless Global Interrupts are enabled.
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