📄 cmx_pwm_chan.lis
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0000 IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
0000 RAM_CHANGE_PAGE_MODE FLAG_PGMODE_10b ; LMM with independent IndexPage
0000 ENDIF ; PGMODE FREE
0000 ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
0000 macro RAM_X_POINTS_TO_STACKPAGE
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 or F, FLAG_PGMODE_01b
0000 ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
0000 macro RAM_X_POINTS_TO_INDEXPAGE
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 and F, ~FLAG_PGMODE_01b
0000 ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
0000 macro RAM_PROLOGUE( ACTUAL_CLASS )
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_1 )
0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_1
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_2 )
0000 IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
0000 RAM_X_POINTS_TO_STACKPAGE ; exit native paging mode!
0000 ENDIF
0000 ENDIF ; RAM_USE_CLASS_2
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_3 )
0000 IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
0000 RAM_X_POINTS_TO_INDEXPAGE ; exit native paging mode!
0000 ENDIF
0000 ENDIF ; RAM_USE_CLASS_3
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_4 )
0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_4
0000
0000 macro RAM_EPILOGUE( ACTUAL_CLASS )
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_1 )
0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_1
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_2 )
0000 RAM_RESTORE_NATIVE_PAGING
0000 ENDIF ; RAM_USE_CLASS_2
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_3 )
0000 RAM_RESTORE_NATIVE_PAGING
0000 ENDIF ; RAM_USE_CLASS_3
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_4 )
0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_4
0000
0000 macro REG_PRESERVE( IOReg )
0000 mov A, reg[ @IOReg ]
0000 push A
0000 macro REG_RESTORE( IOReg )
0000 pop A
0000 mov reg[ @IOReg ], A
0000 macro ISR_PRESERVE_PAGE_POINTERS
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 REG_PRESERVE CUR_PP
0000 REG_PRESERVE IDX_PP
0000 REG_PRESERVE MVR_PP
0000 REG_PRESERVE MVW_PP
0000 ENDIF
0000 macro ISR_RESTORE_PAGE_POINTERS
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 REG_RESTORE MVW_PP
0000 REG_RESTORE MVR_PP
0000 REG_RESTORE IDX_PP
0000 REG_RESTORE CUR_PP
0000 ENDIF
0020 PWM_High: equ 20h
0002 PWM_Low: equ 2h
0000
00E0 ADC10_ADCIntReg: equ 0e0h
00DA ADC10_ADCClrIntReg: equ 0dah
0004 ADC10_ADCMask: equ 04h
00E1 ADC10_CNTIntReg: equ 0e1h
00DB ADC10_CNTClrIntReg: equ 0dbh
0001 ADC10_CNTMask: equ 01h
0000
0000 ADC10_OFF: equ 0
0001 ADC10_ON: equ 1
0000
0000 ;--------------------------------------------------
0000 ; Registers Address Constants for ADC10
0000 ;--------------------------------------------------
0000
0001 ADC10_LOWRANGE: equ 01h
0003 ADC10_FULLRANGE: equ 03h
0000
0000 ;--------------------------------------------------
0000 ; Deprecated:
0001 ADC10_LOWPOWER: equ 01h
0003 ADC10_FULLPOWER: equ 03h
0000 ;--------------------------------------------------
0000
0003 ADC10_CAL_VBG: equ 03h
0007 ADC10_CAL_AMUXBUS: equ 07h
0010 ADC10_CAL_P0_0: equ 10h
0090 ADC10_CAL_P0_1: equ 90h
0014 ADC10_CAL_P0_2: equ 14h
0091 ADC10_CAL_P0_3: equ 91h
0018 ADC10_CAL_P0_4: equ 18h
0092 ADC10_CAL_P0_5: equ 92h
001C ADC10_CAL_P0_6: equ 1Ch
0093 ADC10_CAL_P0_7: equ 93h
0000
0000
0084 ADC10_ASE_CR0: equ 84h
0076 ADC10_ACE_CR1: equ 76h
0077 ADC10_ACE_CR2: equ 77h
0069 ADC10_ADC_CR: equ 69h
00E6 ADC10_ADC_TR: equ e6h
0000
0020 ADC10_CNT_FN: equ 20h
0021 ADC10_CNT_IN: equ 21h
0022 ADC10_CNT_OUT: equ 22h
0020 ADC10_CNT_DR0: equ 20h
0021 ADC10_CNT_DR1: equ 21h
0022 ADC10_CNT_DR2: equ 22h
0023 ADC10_CNT_CR0: equ 23h
0000
0000
0000 AMUX8_MUX_COL: equ 0
0003 AMUX8_MUX_MASK: equ (03 << (0*2))
0000
0000 AMUX8_PORT0_0: equ 0h
0001 AMUX8_PORT0_1: equ 1h
0002 AMUX8_PORT0_2: equ 2h
0003 AMUX8_PORT0_3: equ 3h
0004 AMUX8_PORT0_4: equ 4h
0005 AMUX8_PORT0_5: equ 5h
0006 AMUX8_PORT0_6: equ 6h
0007 AMUX8_PORT0_7: equ 7h
0000
0000 ; end of file AMUX8.inc
00C0 FLAG_PGMODE_MASK: equ C0h ; Paging control for > 256 bytes of RAM
0000 FLAG_PGMODE_0: equ 00h ; Direct to Page 0, indexed to Page 0
0040 FLAG_PGMODE_1: equ 40h ; Direct to Page 0, indexed to STK_PP page
0080 FLAG_PGMODE_2: equ 80h ; Direct to CUR_PP page, indexed to IDX_PP page
00C0 FLAG_PGMODE_3: equ C0h ; Direct to CUR_PP page, indexed to STK_PP page
0000 FLAG_PGMODE_00b: equ 00h ; Same as PGMODE_0
0040 FLAG_PGMODE_01b: equ 40h ; Same as PGMODE_1
0080 FLAG_PGMODE_10b: equ 80h ; Same as PGMODE_2
00C0 FLAG_PGMODE_11b: equ C0h ; Same as PGMODE_3
0010 FLAG_XIO_MASK: equ 10h ; I/O Bank select for register space
0008 FLAG_SUPER: equ 08h ; Supervisor Mode
0004 FLAG_CARRY: equ 04h ; Carry Condition Flag
0002 FLAG_ZERO: equ 02h ; Zero Condition Flag
0001 FLAG_GLOBAL_IE: equ 01h ; Glogal Interrupt Enable
0000
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 0
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)
0001 PRT0IE: equ 01h ; Port 0 Interrupt Enable Register (RW)
0002 PRT0GS: equ 02h ; Port 0 Global Select Register (RW)
0003 PRT0DM2: equ 03h ; Port 0 Drive Mode 2 (RW)
0000 ; Port 1
0004 PRT1DR: equ 04h ; Port 1 Data Register (RW)
0005 PRT1IE: equ 05h ; Port 1 Interrupt Enable Register (RW)
0006 PRT1GS: equ 06h ; Port 1 Global Select Register (RW)
0007 PRT1DM2: equ 07h ; Port 1 Drive Mode 2 (RW)
0000 ; Port 2
0008 PRT2DR: equ 08h ; Port 2 Data Register (RW)
0009 PRT2IE: equ 09h ; Port 2 Interrupt Enable Register (RW)
000A PRT2GS: equ 0Ah ; Port 2 Global Select Register (RW)
000B PRT2DM2: equ 0Bh ; Port 2 Drive Mode 2 (RW)
0000 ; Port 3
000C PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
000D PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (RW)
000E PRT3GS: equ 0Eh ; Port 3 Global Select Register (RW)
000F PRT3DM2: equ 0Fh ; Port 3 Drive Mode 2 (RW)
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Digital PSoC block 00, Basic Type B
0020 DBB00DR0: equ 20h ; data register 0 (#)
0021 DBB00DR1: equ 21h ; data register 1 (W)
0022 DBB00DR2: equ 22h ; data register 2 (RW)
0023 DBB00CR0: equ 23h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 01, Basic Type B
0024 DBB01DR0: equ 24h ; data register 0 (#)
0025 DBB01DR1: equ 25h ; data register 1 (W)
0026 DBB01DR2: equ 26h ; data register 2 (RW)
0027 DBB01CR0: equ 27h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 02, Communications Type B
0028 DCB02DR0: equ 28h ; data register 0 (#)
0029 DCB02DR1: equ 29h ; data register 1 (W)
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