📄 interrrupt.lst
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(0488) ;
00C9: 62 E3 00 MOV REG[227],0 (0489) M8C_ClearWDT ; Clear the watchdog for long inits
00CC: 08 PUSH A (0490) push A
00CD: 28 ROMX (0491) romx ; MSB of RAM addr (CPU.A <- *pXIData)
00CE: 60 D5 MOV REG[213],A (0492) mov reg[MVW_PP], A ; for use with MVI write operations
00D0: 74 INC A (0493) inc A ; End of Struct List? (MSB==0xFF?)
00D1: A0 4B JZ 0x011D (0494) jz .C_RTE_WrapUp ; Yes, C runtime environment complete
00D3: 18 POP A (0495) pop A ; restore pXIData to [A,X]
00D4: 75 INC X (0496) inc X ; pXIData++
00D5: 09 00 ADC A,0 (0497) adc A, 0
00D7: 08 PUSH A (0498) push A
00D8: 28 ROMX (0499) romx ; LSB of RAM addr (CPU.A <- *pXIData)
00D9: 53 0F MOV [__r0],A (0500) mov [__r0], A ; RAM Addr now in [reg[MVW_PP],[__r0]]
00DB: 18 POP A (0501) pop A ; restore pXIData to [A,X]
00DC: 75 INC X (0502) inc X ; pXIData++ (point to size)
00DD: 09 00 ADC A,0 (0503) adc A, 0
00DF: 08 PUSH A (0504) push A
00E0: 28 ROMX (0505) romx ; Get the size (CPU.A <- *pXIData)
00E1: A0 1C JZ 0x00FE (0506) jz .ClearRAMBlockToZero ; If Size==0, then go clear RAM
00E3: 53 0E MOV [__r1],A (0507) mov [__r1], A ; else downcount in __r1
00E5: 18 POP A (0508) pop A ; restore pXIData to [A,X]
(0509)
(0510) .CopyNextByteLoop:
(0511) ; For each byte in the structure's array member, copy from flash to RAM.
(0512) ; Assert: pXIData in [A,X] points to previous byte of flash source;
(0513) ; [reg[MVW_PP],[__r0]] points to next RAM destination;
(0514) ; __r1 holds a non-zero count of the number of bytes remaining.
(0515) ;
00E6: 75 INC X (0516) inc X ; pXIData++ (point to next data byte)
00E7: 09 00 ADC A,0 (0517) adc A, 0
00E9: 08 PUSH A (0518) push A
00EA: 28 ROMX (0519) romx ; Get the data value (CPU.A <- *pXIData)
00EB: 3F 0F MVI [__r0],A (0520) mvi [__r0], A ; Transfer the data to RAM
00ED: 47 0F FF TST [15],255 (0521) tst [__r0], 0xff ; Check for page crossing
00F0: B0 06 JNZ 0x00F7 (0522) jnz .CopyLoopTail ; No crossing, keep going
00F2: 5D D5 MOV A,REG[213] (0523) mov A, reg[ MVW_PP] ; If crossing, bump MVW page reg
00F4: 74 INC A (0524) inc A
00F5: 60 D5 MOV REG[213],A (0525) mov reg[ MVW_PP], A
(0526) .CopyLoopTail:
00F7: 18 POP A (0527) pop A ; restore pXIData to [A,X]
00F8: 7A 0E DEC [__r1] (0528) dec [__r1] ; End of this array in flash?
00FA: BF EB JNZ 0x00E6 (0529) jnz .CopyNextByteLoop ; No, more bytes to copy
00FC: 8F C9 JMP 0x00C6 (0530) jmp .AccessNextStructLoop ; Yes, initialize another RAM block
(0531)
(0532) .ClearRAMBlockToZero:
00FE: 18 POP A (0533) pop A ; restore pXIData to [A,X]
00FF: 75 INC X (0534) inc X ; pXIData++ (point to next data byte)
0100: 09 00 ADC A,0 (0535) adc A, 0
0102: 08 PUSH A (0536) push A
0103: 28 ROMX (0537) romx ; Get the run length (CPU.A <- *pXIData)
0104: 53 0E MOV [__r1],A (0538) mov [__r1], A ; Initialize downcounter
0106: 50 00 MOV A,0 (0539) mov A, 0 ; Initialize source data
(0540)
(0541) .ClearRAMBlockLoop:
(0542) ; Assert: [reg[MVW_PP],[__r0]] points to next RAM destination and
(0543) ; __r1 holds a non-zero count of the number of bytes remaining.
(0544) ;
0108: 3F 0F MVI [__r0],A (0545) mvi [__r0], A ; Clear a byte
010A: 47 0F FF TST [15],255 (0546) tst [__r0], 0xff ; Check for page crossing
010D: B0 08 JNZ 0x0116 (0547) jnz .ClearLoopTail ; No crossing, keep going
010F: 5D D5 MOV A,REG[213] (0548) mov A, reg[ MVW_PP] ; If crossing, bump MVW page reg
0111: 74 INC A (0549) inc A
0112: 60 D5 MOV REG[213],A (0550) mov reg[ MVW_PP], A
0114: 50 00 MOV A,0 (0551) mov A, 0 ; Restore the zero used for clearing
(0552) .ClearLoopTail:
0116: 7A 0E DEC [__r1] (0553) dec [__r1] ; Was this the last byte?
0118: BF EF JNZ 0x0108 (0554) jnz .ClearRAMBlockLoop ; No, continue
011A: 18 POP A (0555) pop A ; Yes, restore pXIData to [A,X] and
011B: 8F AA JMP 0x00C6 (0556) jmp .AccessNextStructLoop ; initialize another RAM block
(0557)
(0558) .C_RTE_WrapUp:
011D: 18 POP A (0559) pop A ; balance stack
(0560)
(0561) ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
(0562)
(0563) C_RTE_Done:
(0564)
(0565) ENDIF ; C_LANGUAGE_SUPPORT
(0566)
(0567) ;-------------------------------
(0568) ; Voltage Stabilization for SMP
(0569) ;-------------------------------
(0570)
(0571) IF ( POWER_SETTING & POWER_SET_5V0) ; 5.0V Operation
(0572) IF ( SWITCH_MODE_PUMP ^ 1 ) ; SMP is operational
(0573) ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(0574) ; When using the SMP at 5V, we must wait for Vdd to slew from 3.1V to
(0575) ; 5V before enabling the Precision Power-On Reset (PPOR).
(0576) ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(0577) or reg[INT_MSK0],INT_MSK0_SLEEP
(0578) M8C_SetBank1
(0579) and reg[OSC_CR0], ~OSC_CR0_SLEEP
(0580) or reg[OSC_CR0], OSC_CR0_SLEEP_512Hz
(0581) M8C_SetBank0
(0582) M8C_ClearWDTAndSleep ; Restart the sleep timer
(0583) mov reg[INT_VC], 0 ; Clear all pending interrupts
(0584) .WaitFor2ms:
(0585) tst reg[INT_CLR0], INT_MSK0_SLEEP ; Test the SleepTimer Interrupt Status
(0586) jz .WaitFor2ms ; Branch fails when 2 msec has passed
(0587) ENDIF ; SMP is operational
(0588) ENDIF ; 5.0V Operation
(0589)
(0590) ;-------------------------------
(0591) ; Set Power-On Reset (POR) Level
(0592) ;-------------------------------
011E: 71 10 OR F,16 (0593) M8C_SetBank1
(0594)
(0595) IF (POWER_SETTING & POWER_SET_5V0) ; 5.0V Operation?
(0596) IF (POWER_SETTING & POWER_SET_SLOW_IMO) ; and Slow Mode?
(0597) ELSE ; No, fast mode
(0598) IF ( CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz ) ; As fast as 24MHz?
(0599) ; no, set midpoint POR in user code, if desired
(0600) ELSE ; 24HMz ;
(0601) or reg[VLT_CR], VLT_CR_POR_HIGH ; yes, highest POR trip point required
(0602) ENDIF ; 24MHz
(0603) ENDIF ; Slow Mode
(0604) ENDIF ; 5.0V Operation
(0605)
0120: 70 EF AND F,239 (0606) M8C_SetBank0
(0607)
(0608) ;----------------------------
(0609) ; Wrap up and invoke "main"
(0610) ;----------------------------
(0611)
(0612) ; Disable the Sleep interrupt that was used for timing above. In fact,
(0613) ; no interrupts should be enabled now, so may as well clear the register.
(0614) ;
0122: 62 E0 00 MOV REG[224],0 (0615) mov reg[INT_MSK0],0
(0616)
(0617) ; Everything has started OK. Now select requested CPU & sleep frequency.
(0618) ; And put decimator in full mode so it does not consume too much current.
(0619) ;
0125: 71 10 OR F,16 (0620) M8C_SetBank1
0127: 62 E0 00 MOV REG[224],0 (0621) mov reg[OSC_CR0],(SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | CPU_CLOCK_JUST)
012A: 43 E7 80 OR REG[231],128 (0622) or reg[DEC_CR2],80h ; Put decimator in full mode
012D: 70 EF AND F,239 (0623) M8C_SetBank0
(0624)
(0625) ; Global Interrupt are NOT enabled, this should be done in main().
(0626) ; LVD is set but will not occur unless Global Interrupts are enabled.
(0627) ; Global Interrupts should be enabled as soon as possible in main().
(0628) ;
012F: 62 E2 00 MOV REG[226],0 (0629) mov reg[INT_VC],0 ; Clear any pending interrupts which may
(0630) ; have been set during the boot process.
(0631) IF (TOOLCHAIN & HITECH)
(0632) ljmp startup ; Jump to C compiler startup code
(0633) ELSE
(0634) IF ENABLE_LJMP_TO_MAIN
(0635) ljmp _main ; goto main (no return)
(0636) ELSE
0132: 7C 04 08 LCALL _main (0637) lcall _main ; call main
(0638) .Exit:
0135: 8F FF JMP 0x0135 (0639) jmp .Exit ; Wait here after return till power-off or reset
(0640) ENDIF
(0641) ENDIF ; TOOLCHAIN
(0642)
(0643) ;---------------------------------
(0644) ; Library Access to Global Parms
(0645) ;---------------------------------
(0646) ;
(0647) bGetPowerSetting:
(0648) _bGetPowerSetting:
(0649) ; Returns value of POWER_SETTING in the A register.
(0650) ; No inputs. No Side Effects.
(0651) ;
0137: 50 10 MOV A,16 (0652) mov A, POWER_SETTING
0139: 7F RET (0653) ret
013A: 30 HALT
013B: 30 HALT
013C: 30 HALT
013D: 30 HALT
013E: 30 HALT
013F: 30 HALT
0140: 30 HALT
0141: 30 HALT
0142: 30 HALT
0143: 30 HALT
0144: 30 HALT
0145: 30 HALT
0146: 30 HALT
0147: 30 HALT
0148: 30 HALT
0149: 30 HALT
014A: 30 HALT
014B: 30 HALT
014C: 30 HALT
014D: 30 HALT
014E: 30 HALT
014F: 30 HALT
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