📄 interrrupt.lst
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(0157) org 2Ch ;PSoC Block DCB03 Interrupt Vector
(0158) // call void_handler
002C: 7E RETI (0159) reti
002D: 30 HALT
002E: 30 HALT
002F: 30 HALT
(0160)
(0161) org 30h ;PSoC Block DBB10 Interrupt Vector
(0162) // call void_handler
0030: 7E RETI (0163) reti
0031: 30 HALT
0032: 30 HALT
0033: 30 HALT
(0164)
(0165) org 34h ;PSoC Block DBB11 Interrupt Vector
(0166) // call void_handler
0034: 7E RETI (0167) reti
0035: 30 HALT
0036: 30 HALT
0037: 30 HALT
(0168)
(0169) org 38h ;PSoC Block DCB12 Interrupt Vector
(0170) // call void_handler
0038: 7E RETI (0171) reti
0039: 30 HALT
003A: 30 HALT
003B: 30 HALT
(0172)
(0173) org 3Ch ;PSoC Block DCB13 Interrupt Vector
(0174) // call void_handler
003C: 7E RETI (0175) reti
003D: 30 HALT
003E: 30 HALT
003F: 30 HALT
(0176)
(0177) org 40h ;PSoC Block DBB20 Interrupt Vector
(0178) // call void_handler
0040: 7E RETI (0179) reti
0041: 30 HALT
0042: 30 HALT
0043: 30 HALT
(0180)
(0181) org 44h ;PSoC Block DBB21 Interrupt Vector
(0182) // call void_handler
0044: 7E RETI (0183) reti
0045: 30 HALT
0046: 30 HALT
0047: 30 HALT
(0184)
(0185) org 48h ;PSoC Block DCB22 Interrupt Vector
(0186) // call void_handler
0048: 7E RETI (0187) reti
0049: 30 HALT
004A: 30 HALT
004B: 30 HALT
(0188)
(0189) org 4Ch ;PSoC Block DCB23 Interrupt Vector
(0190) // call void_handler
004C: 7E RETI (0191) reti
004D: 30 HALT
004E: 30 HALT
004F: 30 HALT
(0192)
(0193) org 50h ;PSoC Block DBB30 Interrupt Vector
(0194) // call void_handler
0050: 7E RETI (0195) reti
0051: 30 HALT
0052: 30 HALT
0053: 30 HALT
(0196)
(0197) org 54h ;PSoC Block DBB31 Interrupt Vector
(0198) // call void_handler
0054: 7E RETI (0199) reti
0055: 30 HALT
0056: 30 HALT
0057: 30 HALT
(0200)
(0201) org 58h ;PSoC Block DCB32 Interrupt Vector
(0202) // call void_handler
0058: 7E RETI (0203) reti
0059: 30 HALT
005A: 30 HALT
005B: 30 HALT
(0204)
(0205) org 5Ch ;PSoC Block DCB33 Interrupt Vector
(0206) // call void_handler
005C: 7E RETI (0207) reti
005D: 30 HALT
005E: 30 HALT
005F: 30 HALT
(0208)
(0209) org 60h ;PSoC I2C Interrupt Vector
(0210) // call void_handler
0060: 7E RETI (0211) reti
0061: 30 HALT
0062: 30 HALT
0063: 30 HALT
(0212)
(0213) org 64h ;Sleep Timer Interrupt Vector
(0214) // call void_handler
0064: 7E RETI (0215) reti
0065: 30 HALT
0066: 30 HALT
0067: 30 HALT
(0216)
(0217) ;-----------------------------------------------------------------------------
(0218) ; Start of Execution.
(0219) ;-----------------------------------------------------------------------------
(0220) ; The Supervisory ROM SWBootReset function has already completed the
(0221) ; calibrate1 process, loading trim values for 5 volt operation.
(0222) ;
(0223)
(0224) IF (TOOLCHAIN & HITECH)
(0225) AREA PD_startup(CODE, REL, CON)
(0226) ELSE
(0227) org 68h
(0228) ENDIF
(0229) __Start:
(0230)
(0231) ; initialize SMP values for voltage stabilization, if required,
(0232) ; leaving power-on reset (POR) level at the default (low) level, at
(0233) ; least for now.
(0234) ;
0068: 71 10 OR F,16 (0235) M8C_SetBank1
006A: 62 E3 87 MOV REG[227],135 (0236) mov reg[VLT_CR], SWITCH_MODE_PUMP_JUST | LVD_TBEN_JUST | TRIP_VOLTAGE_JUST
006D: 70 EF AND F,239 (0237) M8C_SetBank0
(0238)
(0239) ; %53%20%46%46% Apply Erratum 001-05137 workaround
006F: 50 20 MOV A,32 (0240) mov A, 20h
0071: 28 ROMX (0241) romx
0072: 50 40 MOV A,64 (0242) mov A, 40h
0074: 28 ROMX (0243) romx
0075: 50 60 MOV A,96 (0244) mov A, 60h
0077: 28 ROMX (0245) romx
(0246) ; %45%20%46%46% End workaround
(0247)
(0248) IF ( WATCHDOG_ENABLE ) ; WDT selected in Global Params
(0249) M8C_EnableWatchDog
(0250) ENDIF
(0251)
(0252) IF ( SELECT_32K )
(0253) or reg[CPU_SCR1], CPU_SCR1_ECO_ALLOWED ; ECO will be used in this project
(0254) ELSE
0078: 41 FE FB AND REG[254],251 (0255) and reg[CPU_SCR1], ~CPU_SCR1_ECO_ALLOWED ; Prevent ECO from being enabled
(0256) ENDIF
(0257)
(0258) ;---------------------------
(0259) ; Set up the Temporary stack
(0260) ;---------------------------
(0261) ; A temporary stack is set up for the SSC instructions.
(0262) ; The real stack start will be assigned later.
(0263) ;
(0264) _stack_start: equ 80h
007B: 50 80 MOV A,128 (0265) mov A, _stack_start ; Set top of stack to end of used RAM
007D: 4E SWAP SP,A (0266) swap SP, A ; This is only temporary if going to LMM
(0267)
(0268) ;-----------------------------------------------
(0269) ; Set Power-related Trim & the AGND Bypass bit.
(0270) ;-----------------------------------------------
(0271)
(0272) IF ( POWER_SETTING & POWER_SET_5V0) ; *** 5.0 Volt operation ***
(0273) IF ( POWER_SETTING & POWER_SET_SLOW_IMO) ; *** 6MHZ Main Oscillator ***
(0274) or reg[CPU_SCR1], CPU_SCR1_SLIMO
(0275) M8SSC_Set2TableTrims 2, SSCTBL2_TRIM_IMO_5V_6MHZ, 1, SSCTBL1_TRIM_BGR_5V, AGND_BYPASS_JUST
(0276) ELSE ; *** 12MHZ Main Oscillator ***
(0277) IF ( AGND_BYPASS )
(0278) ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(0279) ; The 5V trim has already been set, but we need to update the AGNDBYP
(0280) ; bit in the write-only BDG_TR register. Recalculate the register
(0281) ; value using the proper trim values.
(0282) ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(0283) M8SSC_SetTableVoltageTrim 1, SSCTBL1_TRIM_BGR_5V, AGND_BYPASS_JUST
(0284) ENDIF
(0285) ENDIF
(0286) ENDIF ; 5.0 V Operation
(0287)
(0288) IF ( POWER_SETTING & POWER_SET_3V3) ; *** 3.3 Volt operation ***
(0289) IF ( POWER_SETTING & POWER_SET_SLOW_IMO) ; *** 6MHZ Main Oscillator ***
(0290) or reg[CPU_SCR1], CPU_SCR1_SLIMO
(0291) M8SSC_Set2TableTrims 2, SSCTBL2_TRIM_IMO_3V_6MHZ, 1, SSCTBL1_TRIM_BGR_3V, AGND_BYPASS_JUST
(0292) ELSE ; *** 12MHZ Main Oscillator ***
(0293) M8SSC_SetTableTrims 1, SSCTBL1_TRIM_IMO_3V_24MHZ, SSCTBL1_TRIM_BGR_3V, AGND_BYPASS_JUST
(0294) ENDIF
(0295) ENDIF ; 3.3 Volt Operation
(0296)
007E: 55 F8 00 MOV [248],0 (0297) mov [bSSC_KEY1], 0 ; Lock out Flash and Supervisiory operations
0081: 55 F9 00 MOV [249],0 (0298) mov [bSSC_KEYSP], 0
(0299)
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