📄 psocgpioint.lis
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0002 OSC_GOEN_CLK24M: equ 02h ; Enable 24 MHz clock onto GOE[1]
0001 OSC_GOEN_CLK32K: equ 01h ; Enable 32 kHz clock onto GOE[0]
0000
00DE OSC_CR4: equ 0DEh ; Oscillator Control Register 4 (RW)
0003 OSC_CR4_VC3: equ 03h ; MASK: System VC3 Clock source
0000
00DF OSC_CR3: equ 0DFh ; Oscillator Control Register 3 (RW)
0000
00E0 OSC_CR0: equ 0E0h ; System Oscillator Control Register 0 (RW)
0080 OSC_CR0_32K_SELECT: equ 80h ; MASK: Enable/Disable External XTAL Osc
0040 OSC_CR0_PLL_MODE: equ 40h ; MASK: Enable/Disable PLL
0020 OSC_CR0_NO_BUZZ: equ 20h ; MASK: Bandgap always powered/BUZZ bandgap
0018 OSC_CR0_SLEEP: equ 18h ; MASK: Set Sleep timer freq/period
0000 OSC_CR0_SLEEP_512Hz: equ 00h ; Set sleep bits for 1.95ms period
0008 OSC_CR0_SLEEP_64Hz: equ 08h ; Set sleep bits for 15.6ms period
0010 OSC_CR0_SLEEP_8Hz: equ 10h ; Set sleep bits for 125ms period
0018 OSC_CR0_SLEEP_1Hz: equ 18h ; Set sleep bits for 1 sec period
0007 OSC_CR0_CPU: equ 07h ; MASK: Set CPU Frequency
0000 OSC_CR0_CPU_3MHz: equ 00h ; set CPU Freq bits for 3MHz Operation
0001 OSC_CR0_CPU_6MHz: equ 01h ; set CPU Freq bits for 6MHz Operation
0002 OSC_CR0_CPU_12MHz: equ 02h ; set CPU Freq bits for 12MHz Operation
0003 OSC_CR0_CPU_24MHz: equ 03h ; set CPU Freq bits for 24MHz Operation
0004 OSC_CR0_CPU_1d5MHz: equ 04h ; set CPU Freq bits for 1.5MHz Operation
0005 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
0006 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
0007 OSC_CR0_CPU_93d7kHz: equ 07h ; set CPU Freq bits for 93.7kHz Operation
0000
00E1 OSC_CR1: equ 0E1h ; System VC1/VC2 Divider Control Register (RW)
00F0 OSC_CR1_VC1: equ 0F0h ; MASK: System VC1 24MHz/External Clk divider
000F OSC_CR1_VC2: equ 0Fh ; MASK: System VC2 24MHz/External Clk divider
0000
00E2 OSC_CR2: equ 0E2h ; Oscillator Control Register 2 (RW)
0004 OSC_CR2_EXTCLKEN: equ 04h ; MASK: Enable/Disable External Clock
0002 OSC_CR2_IMODIS: equ 02h ; MASK: Enable/Disable System (IMO) Clock Net
0001 OSC_CR2_SYSCLKX2DIS: equ 01h ; MASK: Enable/Disable 48MHz clock source
0000
00E3 VLT_CR: equ 0E3h ; Voltage Monitor Control Register (RW)
0080 VLT_CR_SMP: equ 80h ; MASK: Enable Switch Mode Pump
0030 VLT_CR_PORLEV: equ 30h ; MASK: Mask for Power on Reset level control
0000 VLT_CR_POR_LOW: equ 00h ; Lowest Precision Power-on Reset trip point
0010 VLT_CR_POR_MID: equ 10h ; Middle Precision Power-on Reset trip point
0020 VLT_CR_POR_HIGH: equ 20h ; Highest Precision Power-on Reset trip point
0008 VLT_CR_LVDTBEN: equ 08h ; MASK: Enable the CPU Throttle Back on LVD
0007 VLT_CR_VM: equ 07h ; MASK: Mask for Voltage Monitor level setting
0000 VLT_CR_3V0_POR: equ 00h ; -- deprecated symbols --
0010 VLT_CR_4V5_POR: equ 10h ; deprecated
0020 VLT_CR_4V75_POR: equ 20h ; deprecated
0030 VLT_CR_DISABLE: equ 30h ; deprecated
0000
00E4 VLT_CMP: equ 0E4h ; Voltage Monitor Comparators Register (R)
0004 VLT_CMP_PUMP: equ 04h ; MASK: Vcc below SMP trip level
0002 VLT_CMP_LVD: equ 02h ; MASK: Vcc below LVD trip level
0001 VLT_CMP_PPOR: equ 01h ; MASK: Vcc below PPOR trip level
0000
00E7 DEC_CR2: equ 0E7h ; Decimator Control Register 2 (RW)
00E8 IMO_TR: equ 0E8h ; Internal Main Oscillator Trim Register (W)
00E9 ILO_TR: equ 0E9h ; Internal Low-speed Oscillator Trim (W)
00EA BDG_TR: equ 0EAh ; Band Gap Trim Register (W)
00EB ECO_TR: equ 0EBh ; External Oscillator Trim Register (W)
0000
0000 ;;=============================================================================
0000 ;; M8C System Macros
0000 ;; These macros should be used when their functions are needed.
0000 ;;=============================================================================
0000
0000 ;----------------------------------------------------
0000 ; Swapping Register Banks
0000 ;----------------------------------------------------
0000 macro M8C_SetBank0
0000 and F, ~FLAG_XIO_MASK
0000 macro M8C_SetBank1
0000 or F, FLAG_XIO_MASK
0000 macro M8C_EnableGInt
0000 or F, FLAG_GLOBAL_IE
0000 macro M8C_DisableGInt
0000 and F, ~FLAG_GLOBAL_IE
0000 macro M8C_DisableIntMask
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1 ; enable specified interrupt enable bit
0000 macro M8C_ClearIntFlag
0000 mov reg[@0], ~@1 ; clear specified interrupt enable bit
0000 macro M8C_EnableWatchDog
0000 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then the CPU sleeps forever.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore CPU to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro Suspend_CodeCompressor
0000 or F, 0
0000 macro Resume_CodeCompressor
0000 add SP, 0
0004 Port_1_7_Data_ADDR: equ 4h
0104 Port_1_7_DriveMode_0_ADDR: equ 104h
0105 Port_1_7_DriveMode_1_ADDR: equ 105h
0007 Port_1_7_DriveMode_2_ADDR: equ 7h
0006 Port_1_7_GlobalSelect_ADDR: equ 6h
0106 Port_1_7_IntCtrl_0_ADDR: equ 106h
0107 Port_1_7_IntCtrl_1_ADDR: equ 107h
0005 Port_1_7_IntEn_ADDR: equ 5h
0080 Port_1_7_MASK: equ 80h
0000 ; Port_1_7_Data access macros
0000 ; GetPort_1_7_Data macro, return in a
0000 macro GetPort_1_7_Data
0000 mov a,[Port_1_Data_SHADE]
0000 and a, 80h
0000 macro SetPort_1_7_Data
0000 or [Port_1_Data_SHADE], 80h
0000 mov reg[Port_1_Data], [Port_1_Data_SHADE]
0000 macro ClearPort_1_7_Data
0000 and [Port_1_Data_SHADE], ~80h
0000 mov reg[Port_1_Data], [Port_1_Data_SHADE]
0004 LEDPin_Data_ADDR: equ 4h
0104 LEDPin_DriveMode_0_ADDR: equ 104h
0105 LEDPin_DriveMode_1_ADDR: equ 105h
0007 LEDPin_DriveMode_2_ADDR: equ 7h
0006 LEDPin_GlobalSelect_ADDR: equ 6h
0106 LEDPin_IntCtrl_0_ADDR: equ 106h
0107 LEDPin_IntCtrl_1_ADDR: equ 107h
0005 LEDPin_IntEn_ADDR: equ 5h
0040 LEDPin_MASK: equ 40h
0000 ; LEDPin_Data access macros
0000 ; GetLEDPin_Data macro, return in a
0000 macro GetLEDPin_Data
0000 mov a,[Port_1_Data_SHADE]
0000 and a, 40h
0000 macro SetLEDPin_Data
0000 or [Port_1_Data_SHADE], 40h
0000 mov reg[Port_1_Data], [Port_1_Data_SHADE]
0000 macro ClearLEDPin_Data
0000 and [Port_1_Data_SHADE], ~40h
0000 mov reg[Port_1_Data], [Port_1_Data_SHADE]
export PSoC_GPIO_ISR
;-----------------------------------------------
; Constant Definitions
;-----------------------------------------------
;-----------------------------------------------
; Variable Allocation
;-----------------------------------------------
;@PSoC_UserCode_INIT@ (Do not change this line.)
;---------------------------------------------------
; Insert your custom declarations below this banner
;---------------------------------------------------
;---------------------------------------------------
; Insert your custom declarations above this banner
;---------------------------------------------------
;@PSoC_UserCode_END@ (Do not change this line.)
;-----------⌨️ 快捷键说明
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