psocconfigtbl.lis

塞普拉思(cypress)的电容触摸按键汇编程序.

 0020           OSC_GOEN_VC2:         equ 20h    ; Enable VC2 onto GOE[5]
 0010           OSC_GOEN_VC1:         equ 10h    ; Enable VC1 onto GOE[4]
 0008           OSC_GOEN_SYSCLKX2:    equ 08h    ; Enable 2X SysClk onto GOE[3]
 0004           OSC_GOEN_SYSCLK:      equ 04h    ; Enable 1X SysClk onto GOE[2]
 0002           OSC_GOEN_CLK24M:      equ 02h    ; Enable 24 MHz clock onto GOE[1]
 0001           OSC_GOEN_CLK32K:      equ 01h    ; Enable 32 kHz clock onto GOE[0]
 0000           
 00DE           OSC_CR4:      equ 0DEh          ; Oscillator Control Register 4            (RW)
 0003           OSC_CR4_VC3:          equ 03h    ; MASK: System VC3 Clock source
 0000           
 00DF           OSC_CR3:      equ 0DFh          ; Oscillator Control Register 3            (RW)
 0000           
 00E0           OSC_CR0:      equ 0E0h          ; System Oscillator Control Register 0     (RW)
 0080           OSC_CR0_32K_SELECT:   equ 80h    ; MASK: Enable/Disable External XTAL Osc
 0040           OSC_CR0_PLL_MODE:     equ 40h    ; MASK: Enable/Disable PLL
 0020           OSC_CR0_NO_BUZZ:      equ 20h    ; MASK: Bandgap always powered/BUZZ bandgap
 0018           OSC_CR0_SLEEP:        equ 18h    ; MASK: Set Sleep timer freq/period
 0000           OSC_CR0_SLEEP_512Hz:  equ 00h    ;     Set sleep bits for 1.95ms period
 0008           OSC_CR0_SLEEP_64Hz:   equ 08h    ;     Set sleep bits for 15.6ms period
 0010           OSC_CR0_SLEEP_8Hz:    equ 10h    ;     Set sleep bits for 125ms period
 0018           OSC_CR0_SLEEP_1Hz:    equ 18h    ;     Set sleep bits for 1 sec period
 0007           OSC_CR0_CPU:          equ 07h    ; MASK: Set CPU Frequency
 0000           OSC_CR0_CPU_3MHz:     equ 00h    ;     set CPU Freq bits for 3MHz Operation
 0001           OSC_CR0_CPU_6MHz:     equ 01h    ;     set CPU Freq bits for 6MHz Operation
 0002           OSC_CR0_CPU_12MHz:    equ 02h    ;     set CPU Freq bits for 12MHz Operation
 0003           OSC_CR0_CPU_24MHz:    equ 03h    ;     set CPU Freq bits for 24MHz Operation
 0004           OSC_CR0_CPU_1d5MHz:   equ 04h    ;     set CPU Freq bits for 1.5MHz Operation
 0005           OSC_CR0_CPU_750kHz:   equ 05h    ;     set CPU Freq bits for 750kHz Operation
 0006           OSC_CR0_CPU_187d5kHz: equ 06h    ;     set CPU Freq bits for 187.5kHz Operation
 0007           OSC_CR0_CPU_93d7kHz:  equ 07h    ;     set CPU Freq bits for 93.7kHz Operation
 0000           
 00E1           OSC_CR1:      equ 0E1h          ; System VC1/VC2 Divider Control Register  (RW)
 00F0           OSC_CR1_VC1:          equ 0F0h    ; MASK: System VC1 24MHz/External Clk divider
 000F           OSC_CR1_VC2:          equ 0Fh    ; MASK: System VC2 24MHz/External Clk divider
 0000           
 00E2           OSC_CR2:      equ 0E2h          ; Oscillator Control Register 2            (RW)
 0004           OSC_CR2_EXTCLKEN:     equ 04h    ; MASK: Enable/Disable External Clock
 0002           OSC_CR2_IMODIS:       equ 02h    ; MASK: Enable/Disable System (IMO) Clock Net
 0001           OSC_CR2_SYSCLKX2DIS:  equ 01h    ; MASK: Enable/Disable 48MHz clock source
 0000           
 00E3           VLT_CR:       equ 0E3h          ; Voltage Monitor Control Register         (RW)
 0080           VLT_CR_SMP:           equ 80h    ; MASK: Enable Switch Mode Pump
 0030           VLT_CR_PORLEV:        equ 30h    ; MASK: Mask for Power on Reset level control
 0000           VLT_CR_POR_LOW:       equ 00h    ;   Lowest  Precision Power-on Reset trip point
 0010           VLT_CR_POR_MID:       equ 10h    ;   Middle  Precision Power-on Reset trip point
 0020           VLT_CR_POR_HIGH:      equ 20h    ;   Highest Precision Power-on Reset trip point
 0008           VLT_CR_LVDTBEN:       equ 08h    ; MASK: Enable the CPU Throttle Back on LVD
 0007           VLT_CR_VM:            equ 07h    ; MASK: Mask for Voltage Monitor level setting
 0000           VLT_CR_3V0_POR:       equ 00h    ; -- deprecated symbols --
 0010           VLT_CR_4V5_POR:       equ 10h    ;    deprecated
 0020           VLT_CR_4V75_POR:      equ 20h    ;    deprecated
 0030           VLT_CR_DISABLE:       equ 30h    ;    deprecated
 0000           
 00E4           VLT_CMP:      equ 0E4h          ; Voltage Monitor Comparators Register     (R)
 0004           VLT_CMP_PUMP:         equ 04h    ; MASK: Vcc below SMP trip level
 0002           VLT_CMP_LVD:          equ 02h    ; MASK: Vcc below LVD trip level
 0001           VLT_CMP_PPOR:         equ 01h    ; MASK: Vcc below PPOR trip level
 0000           
 00E7           DEC_CR2:      equ 0E7h          ; Decimator Control Register 2             (RW)
 00E8           IMO_TR:       equ 0E8h          ; Internal Main Oscillator Trim Register   (W)
 00E9           ILO_TR:       equ 0E9h          ; Internal Low-speed Oscillator Trim       (W)
 00EA           BDG_TR:       equ 0EAh          ; Band Gap Trim Register                   (W)
 00EB           ECO_TR:       equ 0EBh          ; External Oscillator Trim Register        (W)
 0000           
 0000           ;;=============================================================================
 0000           ;;      M8C System Macros
 0000           ;;  These macros should be used when their functions are needed.
 0000           ;;=============================================================================
 0000           
 0000           ;----------------------------------------------------
 0000           ;  Swapping Register Banks
 0000           ;----------------------------------------------------
 0000               macro M8C_SetBank0
 0000               and   F, ~FLAG_XIO_MASK
 0000               macro M8C_SetBank1
 0000               or    F, FLAG_XIO_MASK
 0000               macro M8C_EnableGInt
 0000               or    F, FLAG_GLOBAL_IE
 0000               macro M8C_DisableGInt
 0000               and   F, ~FLAG_GLOBAL_IE
 0000               macro M8C_DisableIntMask
 0000               and   reg[@0], ~@1              ; disable specified interrupt enable bit
 0000               macro M8C_EnableIntMask
 0000               or    reg[@0], @1               ; enable specified interrupt enable bit
 0000               macro M8C_ClearIntFlag
 0000               mov   reg[@0], ~@1              ; clear specified interrupt enable bit
 0000               macro M8C_EnableWatchDog
 0000               and   reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
 0000               macro M8C_ClearWDT
 0000               mov   reg[RES_WDT], 00h
 0000               macro M8C_ClearWDTAndSleep
 0000               mov   reg[RES_WDT], 38h
 0000               macro M8C_Stall
 0000               or    reg[ASY_CR], ASY_CR_SYNCEN
 0000               macro M8C_Unstall
 0000               and   reg[ASY_CR], ~ASY_CR_SYNCEN
 0000               macro M8C_Sleep
 0000               or    reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
 0000               ; The next instruction to be executed depends on the state of the
 0000               ; various interrupt enable bits. If some interrupts are enabled
 0000               ; and the global interrupts are disabled, the next instruction will
 0000               ; be the one that follows the invocation of this macro. If global
 0000               ; interrupts are also enabled then the next instruction will be
 0000               ; from the interrupt vector table. If no interrupts are enabled
 0000               ; then the CPU sleeps forever.
 0000               macro M8C_Stop
 0000               ; In general, you probably don't want to do this, but here's how:
 0000               or    reg[CPU_SCR0], CPU_SCR0_STOP_MASK
 0000               ; Next instruction to be executed is located in the interrupt
 0000               ; vector table entry for Power-On Reset.
 0000               macro M8C_Reset
 0000               ; Restore CPU to the power-on reset state.
 0000               mov A, 0
 0000               SSC
 0000               ; Next non-supervisor instruction will be at interrupt vector 0.
 0000               macro Suspend_CodeCompressor
 0000               or   F, 0
 0000               macro Resume_CodeCompressor
 0000               add  SP, 0
                export LoadConfigTBL_button_led
                AREA psoc_config(rom, rel)
 0000           LoadConfigTBL_button_led:
 0000           ;  Ordered Global Register values
 0000 7110          or    F, FLAG_XIO_MASK
 0002 620000            mov     reg[00h], 00h           ; Port_0_DriveMode_0 register (PRT0DM0)
 0005 6201FF            mov     reg[01h], ffh           ; Port_0_DriveMode_1 register (PRT0DM1)
 0008 70EF          and   F, ~FLAG_XIO_MASK
 000A 6203FF            mov     reg[03h], ffh           ; Port_0_DriveMode_2 register (PRT0DM2)
 000D 620200            mov     reg[02h], 00h           ; Port_0_GlobalSelect register (PRT0GS)
 0010 7110          or    F, FLAG_XIO_MASK
 0012 620200            mov     reg[02h], 00h           ; Port_0_IntCtrl_0 register (PRT0IC0)
 0015 620300            mov     reg[03h], 00h           ; Port_0_IntCtrl_1 register (PRT0IC1)
 0018 70EF          and   F, ~FLAG_XIO_MASK
 001A 620100            mov     reg[01h], 00h           ; Port_0_IntEn register (PRT0IE)
 001D 7110          or    F, FLAG_XIO_MASK
 001F 6204C0            mov     reg[04h], c0h           ; Port_1_DriveMode_0 register (PRT1DM0)
 0022 6205BF            mov     reg[05h], bfh           ; Port_1_DriveMode_1 register (PRT1DM1)
 0025 70EF          and   F, ~FLAG_XIO_MASK
 0027 62073F            mov     reg[07h], 3fh           ; Port_1_DriveMode_2 register (PRT1DM2)
 002A 620600            mov     reg[06h], 00h           ; Port_1_GlobalSelect register (PRT1GS)
 002D 7110          or    F, FLAG_XIO_MASK
 002F 620600            mov     reg[06h], 00h           ; Port_1_IntCtrl_0 register (PRT1IC0)
 0032 620700            mov     reg[07h], 00h           ; Port_1_IntCtrl_1 register (PRT1IC1)
 0035 70EF          and   F, ~FLAG_XIO_MASK
 0037 620500            mov     reg[05h], 00h           ; Port_1_IntEn register (PRT1IE)
 003A 7110          or    F, FLAG_XIO_MASK
 003C 620800            mov     reg[08h], 00h           ; Port_2_DriveMode_0 register (PRT2DM0)
 003F 6209FF            mov     reg[09h], ffh           ; Port_2_DriveMode_1 register (PRT2DM1)
 0042 70EF          and   F, ~FLAG_XIO_MASK
 0044 620BFF            mov     reg[0bh], ffh           ; Port_2_DriveMode_2 register (PRT2DM2)
 0047 620A00            mov     reg[0ah], 00h           ; Port_2_GlobalSelect register (PRT2GS)
 004A 7110          or    F, FLAG_XIO_MASK
 004C 620A00            mov     reg[0ah], 00h           ; Port_2_IntCtrl_0 register (PRT2IC0)
 004F 620B00            mov     reg[0bh], 00h           ; Port_2_IntCtrl_1 register (PRT2IC1)
 0052 70EF          and   F, ~FLAG_XIO_MASK
 0054 620900            mov     reg[09h], 00h           ; Port_2_IntEn register (PRT2IE)
 0057 7110          or    F, FLAG_XIO_MASK
 0059 620C00            mov     reg[0ch], 00h           ; Port_3_DriveMode_0 register (PRT3DM0)
 005C 620D00            mov     reg[0dh], 00h           ; Port_3_DriveMode_1 register (PRT3DM1)
 005F 70EF          and   F, ~FLAG_XIO_MASK
 0061 620F00            mov     reg[0fh], 00h           ; Port_3_DriveMode_2 register (PRT3DM2)
 0064 620E00            mov     reg[0eh], 00h           ; Port_3_GlobalSelect register (PRT3GS)
 0067 7110          or    F, FLAG_XIO_MASK
 0069 620E00            mov     reg[0eh], 00h           ; Port_3_IntCtrl_0 register (PRT3IC0)
 006C 620F00            mov     reg[0fh], 00h           ; Port_3_IntCtrl_1 register (PRT3IC1)
 006F 70EF          and   F, ~FLAG_XIO_MASK
 0071 620D00            mov     reg[0dh], 00h           ; Port_3_IntEn register (PRT3IE)
 0074 7110          or    F, FLAG_XIO_MASK
 0076 621000            mov     reg[10h], 00h           ; Port_4_DriveMode_0 register (PRT4DM0)
 0079 621100            mov     reg[11h], 00h           ; Port_4_DriveMode_1 register (PRT4DM1)
 007C 70EF          and   F, ~FLAG_XIO_MASK
 007E 621300            mov     reg[13h], 00h           ; Port_4_DriveMode_2 register (PRT4DM2)
 0081 621200            mov     reg[12h], 00h           ; Port_4_GlobalSelect register (PRT4GS)
 0084 7110          or    F,