📄 psocconfigtbl.lis
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0000 I2C_CFG_CLK_RATE_100K: equ 00h ; MASK: I2C clock set at 100K
0004 I2C_CFG_CLK_RATE_400K: equ 04h ; MASK: I2C clock set at 400K
0008 I2C_CFG_CLK_RATE_50K: equ 08h ; MASK: I2C clock set at 50K
000C I2C_CFG_CLK_RATE_1M6: equ 0Ch ; MASK: I2C clock set at 1.6M
000C I2C_CFG_CLK_RATE: equ 0Ch ; MASK: I2C clock rate setting mask
0002 I2C_CFG_PSELECT_MASTER: equ 02h ; MASK: Enable I2C Master
0001 I2C_CFG_PSELECT_SLAVE: equ 01h ; MASK: Enable I2C Slave
0000
00D7 I2C_SCR: equ 0D7h ; I2C Status and Control Register (#)
0080 I2C_SCR_BUSERR: equ 80h ; MASK: I2C Bus Error detected (RC)
0040 I2C_SCR_LOSTARB: equ 40h ; MASK: I2C Arbitration lost (RC)
0020 I2C_SCR_STOP: equ 20h ; MASK: I2C Stop detected (RC)
0010 I2C_SCR_ACK: equ 10h ; MASK: ACK the last byte (RW)
0008 I2C_SCR_ADDR: equ 08h ; MASK: Address rcv'd is Slave address (RC)
0004 I2C_SCR_XMIT: equ 04h ; MASK: Set transfer to tranmit mode (RW)
0002 I2C_SCR_LRB: equ 02h ; MASK: Last recieved bit (RC)
0001 I2C_SCR_BYTECOMPLETE: equ 01h ; MASK: Transfer of byte complete (RC)
0000
00D8 I2C_DR: equ 0D8h ; I2C Data Register (RW)
0000
00D9 I2C_MSCR: equ 0D9h ; I2C Master Status and Control Register (#)
0008 I2C_MSCR_BUSY: equ 08h ; MASK: I2C Busy (Start detected) (R)
0004 I2C_MSCR_MODE: equ 04h ; MASK: Start has been generated (R)
0002 I2C_MSCR_RESTART: equ 02h ; MASK: Generate a Restart condition (RW)
0001 I2C_MSCR_START: equ 01h ; MASK: Generate a Start condition (RW)
0000
0000 ;------------------------------------------------
0000 ; System and Global Resource Registers
0000 ;------------------------------------------------
00DA INT_CLR0: equ 0DAh ; Interrupt Clear Register 0 (RW)
0000 ; Use INT_MSK0 bit field masks
00DB INT_CLR1: equ 0DBh ; Interrupt Clear Register 1 (RW)
0000 ; Use INT_MSK1 bit field masks
00DC INT_CLR2: equ 0DCh ; Interrupt Clear Register 2 (RW)
0000 ; Use INT_MSK2 bit field masks
00DD INT_CLR3: equ 0DDh ; Interrupt Clear Register 3 (RW)
0000 ; Use INT_MSK3 bit field masks
0000
00DE INT_MSK3: equ 0DEh ; I2C and Software Mask Register (RW)
0080 INT_MSK3_ENSWINT: equ 80h ; MASK: enable/disable SW interrupt
0001 INT_MSK3_I2C: equ 01h ; MASK: enable/disable I2C interrupt
0000
00DF INT_MSK2: equ 0DFh ; Digital PSoC block Mask Register (RW)
0080 INT_MSK2_DCB33: equ 80h ; MASK: enable/disable DCB33 block interrupt
0040 INT_MSK2_DCB32: equ 40h ; MASK: enable/disable DCB32 block interrupt
0020 INT_MSK2_DBB31: equ 20h ; MASK: enable/disable DBB31 block interrupt
0010 INT_MSK2_DBB30: equ 10h ; MASK: enable/disable DBB30 block interrupt
0008 INT_MSK2_DCB23: equ 08h ; MASK: enable/disable DCB23 block interrupt
0004 INT_MSK2_DCB22: equ 04h ; MASK: enable/disable DCB22 block interrupt
0002 INT_MSK2_DBB21: equ 02h ; MASK: enable/disable DBB21 block interrupt
0001 INT_MSK2_DBB20: equ 01h ; MASK: enable/disable DBB20 block interrupt
0000
00E0 INT_MSK0: equ 0E0h ; General Interrupt Mask Register (RW)
0080 INT_MSK0_VC3: equ 80h ; MASK: enable/disable VC3 interrupt
0040 INT_MSK0_SLEEP: equ 40h ; MASK: enable/disable sleep interrupt
0020 INT_MSK0_GPIO: equ 20h ; MASK: enable/disable GPIO interrupt
0010 INT_MSK0_ACOLUMN_3: equ 10h ; MASK: enable/disable Analog col 3 interrupt
0008 INT_MSK0_ACOLUMN_2: equ 08h ; MASK: enable/disable Analog col 2 interrupt
0004 INT_MSK0_ACOLUMN_1: equ 04h ; MASK: enable/disable Analog col 1 interrupt
0002 INT_MSK0_ACOLUMN_0: equ 02h ; MASK: enable/disable Analog col 0 interrupt
0001 INT_MSK0_VOLTAGE_MONITOR: equ 01h ; MASK: enable/disable Volts interrupt
0000
00E1 INT_MSK1: equ 0E1h ; Digital PSoC block Mask Register (RW)
0080 INT_MSK1_DCB13: equ 80h ; MASK: enable/disable DCB13 block interrupt
0040 INT_MSK1_DCB12: equ 40h ; MASK: enable/disable DCB12 block interrupt
0020 INT_MSK1_DBB11: equ 20h ; MASK: enable/disable DBB11 block interrupt
0010 INT_MSK1_DBB10: equ 10h ; MASK: enable/disable DBB10 block interrupt
0008 INT_MSK1_DCB03: equ 08h ; MASK: enable/disable DCB03 block interrupt
0004 INT_MSK1_DCB02: equ 04h ; MASK: enable/disable DCB02 block interrupt
0002 INT_MSK1_DBB01: equ 02h ; MASK: enable/disable DBB01 block interrupt
0001 INT_MSK1_DBB00: equ 01h ; MASK: enable/disable DBB00 block interrupt
0000
00E2 INT_VC: equ 0E2h ; Interrupt vector register (RC)
00E3 RES_WDT: equ 0E3h ; Watch Dog Timer Register (W)
0000
0000 ; DECIMATOR Registers
00E4 DEC_DH: equ 0E4h ; Data Register (high byte) (RC)
00E5 DEC_DL: equ 0E5h ; Data Register ( low byte) (RC)
00E6 DEC_CR0: equ 0E6h ; Data Control Register 0 (RW)
00E7 DEC_CR1: equ 0E7h ; Data Control Register 1 (RW)
0000 ; Also see DEC_CR2 in bank 1
0000
0000 ; Multiplier and MAC (Multiply/Accumulate) Unit
0000 // Compatibility Set: Maps onto MAC0
00E8 MUL_X: equ 0E8h ; Multiplier X Register (write) (W)
00E9 MUL_Y: equ 0E9h ; Multiplier Y Register (write) (W)
00EA MUL_DH: equ 0EAh ; Multiplier Result Data (high byte read) (R)
00EB MUL_DL: equ 0EBh ; Multiplier Result Data ( low byte read) (R)
00EC MAC_X: equ 0ECh ; write = MAC X register [also see ACC_DR1]
00EC ACC_DR1: equ MAC_X ; read = MAC Accumulator, byte 1 (RW)
00ED MAC_Y: equ 0EDh ; write = MAC Y register [also see ACC_DR0]
00ED ACC_DR0: equ MAC_Y ; read = MAC Accumulator, byte 0 (RW)
00EE MAC_CL0: equ 0EEh ; write = MAC Clear Accum [also see ACC_DR3]
00EE ACC_DR3: equ MAC_CL0 ; read = MAC Accumulator, byte 3 (RW)
00EF MAC_CL1: equ 0EFh ; write = MAC Clear Accum [also see ACC_DR2]
00EF ACC_DR2: equ MAC_CL1 ; read = MAC Accumulator, byte 2 (RW)
0000
0000 // Multiply/Accumulate Unit 0
00E8 MUL0_X: equ 0E8h ; Multiplier 0 X Register (write) (W)
00E9 MUL0_Y: equ 0E9h ; Multiplier 0 Y Register (write) (W)
00EA MUL0_DH: equ 0EAh ; Multiplier 0 Result Data (high byte read)(R)
00EB MUL0_DL: equ 0EBh ; Multiplier 0 Result Data ( low byte read)(R)
00EC MAC0_X: equ 0ECh ; write = MAC 0 X register [also see ACC_DR1]
00EC ACC0_DR1: equ MAC0_X ; read = MAC 0 Accumulator, byte 1 (RW)
00ED MAC0_Y: equ 0EDh ; write = MAC 0 Y register [also see ACC_DR0]
00ED ACC0_DR0: equ MAC0_Y ; read = MAC 0 Accumulator, byte 0 (RW)
00EE MAC0_CL0: equ 0EEh ; write = MAC 0 Clear Accum [also see ACC_DR3]
00EE ACC0_DR3: equ MAC0_CL0 ; read = MAC 0 Accumulator, byte 3 (RW)
00EF MAC0_CL1: equ 0EFh ; write = MAC 0 Clear Accum [also see ACC_DR2]
00EF ACC0_DR2: equ MAC0_CL1 ; read = MAC 0 Accumulator, byte 2 (RW)
0000
0000 // Multiply/Accumulate Unit 1
00A8 MUL1_X: equ 0A8h ; Multiplier 1 X Register (write) (W)
00A9 MUL1_Y: equ 0A9h ; Multiplier 1 Y Register (write) (W)
00AA MUL1_DH: equ 0AAh ; Multiplier 1 Result Data (high byte read)(R)
00AB MUL1_DL: equ 0ABh ; Multiplier 1 Result Data ( low byte read)(R)
00AC MAC1_X: equ 0ACh ; write = MAC 1 X register [also see ACC_DR1]
00AC ACC1_DR1: equ MAC1_X ; read = MAC 1 Accumulator, byte 1 (RW)
00AD MAC1_Y: equ 0ADh ; write = MAC 1 Y register [also see ACC_DR0]
00AD ACC1_DR0: equ MAC1_Y ; read = MAC 1 Accumulator, byte 0 (RW)
00AE MAC1_CL0: equ 0AEh ; write = MAC 1 Clear Accum [also see ACC_DR3]
00AE ACC1_DR3: equ MAC1_CL0 ; read = MAC 1 Accumulator, byte 3 (RW)
00AF MAC1_CL1: equ 0AFh ; write = MAC 1 Clear Accum [also see ACC_DR2]
00AF ACC1_DR2: equ MAC1_CL1 ; read = MAC 1 Accumulator, byte 2 (RW)
0000
0000 ;------------------------------------------------------
0000 ; System Status and Control Registers
0000 ;
0000 ; Note: The following registers are mapped into both
0000 ; register bank 0 AND register bank 1.
0000 ;------------------------------------------------------
00F7 CPU_F: equ 0F7h ; CPU Flag Register Access (RO)
0000 ; Use FLAG_ masks defined at top of file
0000
00FE CPU_SCR1: equ 0FEh ; CPU Status and Control Register #1 (#)
0080 CPU_SCR1_IRESS: equ 80h ; MASK: Boot Phase Re-entry bit
0010 CPU_SCR1_SLIMO: equ 10h ; MASK: Slow Main Oscillator Mode
0008 CPU_SCR1_ECO_ALWD_WR: equ 08h ; MASK: flag, ECO allowed has been written
0004 CPU_SCR1_ECO_ALLOWED: equ 04h ; MASK: ECO allowed to be enabled
0001 CPU_SCR1_IRAMDIS: equ 01h ; MASK: Disable RAM initialization on WDR
0000
00FF CPU_SCR0: equ 0FFh ; CPU Status and Control Register #2 (#)
0080 CPU_SCR0_GIE_MASK: equ 80h ; MASK: Global Interrupt Enable shadow
0020 CPU_SCR0_WDRS_MASK: equ 20h ; MASK: Watch Dog Timer Reset
0010 CPU_SCR0_PORS_MASK: equ 10h ; MASK: power-on reset bit PORS
0008 CPU_SCR0_SLEEP_MASK: equ 08h ; MASK: Enable Sleep
0001 CPU_SCR0_STOP_MASK: equ 01h ; MASK: Halt CPU bit
0000
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 1
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 0.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DM0: equ 00h ; Port 0 Drive Mode 0 (RW)
0001 PRT0DM1: equ 01h ; Port 0 Drive Mode 1 (RW)
0002 PRT0IC0: equ 02h ; Port 0 Interrupt Control 0 (RW)
0003 PRT0IC1: equ 03h ; Port 0 Interrupt Control 1 (RW)
0000
0000 ; Port 1
0004 PRT1DM0: equ 04h ; Port 1 Drive Mode 0 (RW)
0005 PRT1DM1: equ 05h ; Port 1 Drive Mode 1 (RW)
0006 PRT1IC0: equ 06h ; Port 1 Interrupt Control 0 (RW)
0007 PRT1IC1: equ 07h ; Port 1 Interrupt Control 1 (RW)
0000
0000 ; Port 2
0008 PRT2DM0: equ 08h ; Port 2 Drive Mode 0 (RW)
0009 PRT2DM1: equ 09h ; Port 2 Drive Mode 1 (RW)
000A PRT2IC0: equ 0Ah ; Port 2 Interrupt Control 0 (RW)
000B PRT2IC1: equ 0Bh ; Port 2 Interrupt Control 1 (RW)
0000
0000 ; Port 3
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