ad_sample.lst
来自「塞普拉思(sypress) 的ad转换应用范例.」· LST 代码 · 共 917 行 · 第 1/5 页
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917 行
00A2: 50 06 MOV A,6
00A4: 00 SWI
00A5: 51 FC MOV A,[252]
00A7: 60 EA MOV REG[234],A
00A9: 70 EF AND F,239
(0276) ELSE ; *** 12MHZ Main Oscillator ***
(0277) IF ( AGND_BYPASS )
(0278) ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(0279) ; The 5V trim has already been set, but we need to update the AGNDBYP
(0280) ; bit in the write-only BDG_TR register. Recalculate the register
(0281) ; value using the proper trim values.
(0282) ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(0283) M8SSC_SetTableVoltageTrim 1, SSCTBL1_TRIM_BGR_5V, AGND_BYPASS_JUST
(0284) ENDIF
(0285) ENDIF
(0286) ENDIF ; 5.0 V Operation
(0287)
(0288) IF ( POWER_SETTING & POWER_SET_3V3) ; *** 3.3 Volt operation ***
(0289) IF ( POWER_SETTING & POWER_SET_SLOW_IMO) ; *** 6MHZ Main Oscillator ***
(0290) or reg[CPU_SCR1], CPU_SCR1_SLIMO
(0291) M8SSC_Set2TableTrims 2, SSCTBL2_TRIM_IMO_3V_6MHZ, 1, SSCTBL1_TRIM_BGR_3V, AGND_BYPASS_JUST
(0292) ELSE ; *** 12MHZ Main Oscillator ***
(0293) M8SSC_SetTableTrims 1, SSCTBL1_TRIM_IMO_3V_24MHZ, SSCTBL1_TRIM_BGR_3V, AGND_BYPASS_JUST
(0294) ENDIF
(0295) ENDIF ; 3.3 Volt Operation
(0296)
00AB: 55 F8 00 MOV [248],0 (0297) mov [bSSC_KEY1], 0 ; Lock out Flash and Supervisiory operations
00AE: 55 F9 00 MOV [249],0 (0298) mov [bSSC_KEYSP], 0
(0299)
(0300) ;---------------------------------------
(0301) ; Initialize Crystal Oscillator and PLL
(0302) ;---------------------------------------
(0303)
(0304) IF ( SELECT_32K & WAIT_FOR_32K )
(0305) ; If the user has requested the External Crystal Oscillator (ECO) then turn it
(0306) ; on and wait for it to stabilize and the system to switch over to it. The PLL
(0307) ; is left off. Set the SleepTimer period is set to 1 sec to time the wait for
(0308) ; the ECO to stabilize.
(0309) ;
(0310) M8C_SetBank1
(0311) mov reg[OSC_CR0], (SELECT_32K_JUST | OSC_CR0_SLEEP_1Hz | OSC_CR0_CPU_12MHz)
(0312) M8C_SetBank0
(0313) M8C_ClearWDTAndSleep ; Reset the sleep timer to get a full second
(0314) or reg[INT_MSK0], INT_MSK0_SLEEP ; Enable latching of SleepTimer interrupt
(0315) mov reg[INT_VC], 0 ; Clear all pending interrupts
(0316) .WaitFor1s:
(0317) tst reg[INT_CLR0], INT_MSK0_SLEEP ; Test the SleepTimer Interrupt Status
(0318) jz .WaitFor1s ; Interrupt will latch but will not dispatch
(0319) ; since interrupts are not globally enabled
(0320) ELSE ; !( SELECT_32K & WAIT_FOR_32K )
(0321) ; Either no ECO, or waiting for stable clock is to be done in main
00B1: 71 10 OR F,16 (0322) M8C_SetBank1
00B3: 62 E0 02 MOV REG[224],2 (0323) mov reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | OSC_CR0_CPU_12MHz)
00B6: 70 EF AND F,239 (0324) M8C_SetBank0
00B8: 62 E3 38 MOV REG[227],56 (0325) M8C_ClearWDTAndSleep ; Reset the watch dog
(0326)
(0327) ENDIF ;( SELECT_32K & WAIT_FOR_32K )
(0328)
(0329) IF ( PLL_MODE )
(0330) ; Crystal is now fully operational (assuming WAIT_FOR_32K was enabled).
(0331) ; Now start up PLL if selected, and wait 16 msec for it to stabilize.
(0332) ;
(0333) M8C_SetBank1
(0334) mov reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | OSC_CR0_SLEEP_64Hz | OSC_CR0_CPU_3MHz)
(0335) M8C_SetBank0
(0336) M8C_ClearWDTAndSleep ; Reset the sleep timer to get full period
(0337) mov reg[INT_VC], 0 ; Clear all pending interrupts
(0338)
(0339) .WaitFor16ms:
(0340) tst reg[INT_CLR0],INT_MSK0_SLEEP ; Test the SleepTimer Interrupt Status
(0341) jz .WaitFor16ms
(0342) M8C_SetBank1 ; continue boot at CPU Speed of SYSCLK/2
(0343) mov reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | OSC_CR0_SLEEP_64Hz | OSC_CR0_CPU_12MHz)
(0344) M8C_SetBank0
(0345)
(0346) IF ( WAIT_FOR_32K )
(0347) ELSE ; !( WAIT_FOR_32K )
(0348) ; Option settings (PLL-Yes, ECO-No) are incompatible - force a syntax error
(0349) ERROR_PSoC Disabling WAIT_FOR_32K requires that the PLL_Lock must be enabled in user code.
(0350) ENDIF ;(WAIT_FOR_32K)
(0351) ENDIF ;(PLL_MODE)
(0352)
(0353) ;------------------------
(0354) ; Close CT leakage path.
(0355) ;------------------------
00BB: 62 71 05 MOV REG[113],5 (0356) mov reg[ACB00CR0], 05h
00BE: 62 75 05 MOV REG[117],5 (0357) mov reg[ACB01CR0], 05h
00C1: 62 79 05 MOV REG[121],5 (0358) mov reg[ACB02CR0], 05h
00C4: 62 7D 05 MOV REG[125],5 (0359) mov reg[ACB03CR0], 05h
(0360)
(0361)
(0362) IF (TOOLCHAIN & HITECH)
(0363) ;---------------------------------------------
(0364) ; HI-TECH initialization: Enter the Large Memory Model, if applicable
(0365) ;---------------------------------------------
(0366) global __Lstackps
(0367) mov a,low __Lstackps
(0368) swap a,sp
(0369)
(0370) IF ( SYSTEM_LARGE_MEMORY_MODEL )
(0371) RAM_SETPAGE_STK SYSTEM_STACK_PAGE ; relocate stack page ...
(0372) RAM_SETPAGE_IDX2STK ; initialize other page pointers
(0373) RAM_SETPAGE_CUR 0
(0374) RAM_SETPAGE_MVW 0
(0375) RAM_SETPAGE_MVR 0
(0376) IF ( SYSTEM_IDXPG_TRACKS_STK_PP ); Now enable paging:
(0377) or F, FLAG_PGMODE_11b ; LMM w/ IndexPage<==>StackPage
(0378) ELSE
(0379) or F, FLAG_PGMODE_10b ; LMM w/ independent IndexPage
(0380) ENDIF ; SYSTEM_IDXPG_TRACKS_STK_PP
(0381) ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
(0382) ELSE
(0383) ;---------------------------------------------
(0384) ; ImageCraft Enter the Large Memory Model, if applicable
(0385) ;---------------------------------------------
(0386) IF ( SYSTEM_LARGE_MEMORY_MODEL )
00C7: 62 D1 07 MOV REG[209],7 (0387) RAM_SETPAGE_STK SYSTEM_STACK_PAGE ; relocate stack page ...
00CA: 50 00 MOV A,0 (0388) mov A, SYSTEM_STACK_BASE_ADDR ; and offset, if any
00CC: 4E SWAP SP,A (0389) swap A, SP
00CD: 62 D3 07 MOV REG[211],7 (0390) RAM_SETPAGE_IDX2STK ; initialize other page pointers
00D0: 62 D0 00 MOV REG[208],0 (0391) RAM_SETPAGE_CUR 0
00D3: 62 D5 00 MOV REG[213],0 (0392) RAM_SETPAGE_MVW 0
00D6: 62 D4 00 MOV REG[212],0 (0393) RAM_SETPAGE_MVR 0
(0394)
(0395) IF ( SYSTEM_IDXPG_TRACKS_STK_PP ); Now enable paging:
00D9: 71 C0 OR F,192 (0396) or F, FLAG_PGMODE_11b ; LMM w/ IndexPage<==>StackPage
(0397) ELSE
(0398) or F, FLAG_PGMODE_10b ; LMM w/ independent IndexPage
(0399) ENDIF ; SYSTEM_IDXPG_TRACKS_STK_PP
(0400) ELSE
(0401) mov A, __ramareas_end ; Set top of stack to end of used RAM
(0402) swap SP, A
(0403) ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
(0404) ENDIF ; TOOLCHAIN
(0405)
(0406) ;-------------------------
(0407) ; Load Base Configuration
(0408) ;-------------------------
(0409) ; Load global parameter settings and load the user modules in the
(0410) ; base configuration. Exceptions: (1) Leave CPU Speed fast as possible
(0411) ; to minimize start up time; (2) We may still need to play with the
(0412) ; Sleep Timer.
(0413) ;
00DB: 7C 03 66 LCALL 0x0366 (0414) lcall LoadConfigInit
(0415)
(0416) ;-----------------------------------
(0417) ; Initialize C Run-Time Environment
(0418) ;-----------------------------------
(0419) IF ( C_LANGUAGE_SUPPORT )
(0420) IF ( SYSTEM_SMALL_MEMORY_MODEL )
(0421) mov A,0 ; clear the 'bss' segment to zero
(0422) mov [__r0],<__bss_start
(0423) BssLoop:
(0424) cmp [__r0],<__bss_end
(0425) jz BssDone
(0426) mvi [__r0],A
(0427) jmp BssLoop
(0428) BssDone:
(0429) mov A,>__idata_start ; copy idata to data segment
(0430) mov X,<__idata_start
(0431) mov [__r0],<__data_start
(0432) IDataLoop:
(0433) cmp [__r0],<__data_end
(0434) jz C_RTE_Done
(0435) push A
(0436) romx
(0437) mvi [__r0],A
(0438) pop A
(0439) inc X
(0440) adc A,0
(0441) jmp IDataLoop
(0442)
(0443) ENDIF ; SYSTEM_SMALL_MEMORY_MODEL
(0444)
(0445) IF ( SYSTEM_LARGE_MEMORY_MODEL )
00DE: 62 D0 00 MOV REG[208],0 (0446) mov reg[CUR_PP], >__r0 ; force direct addr mode instructions
(0447) ; to use the Virtual Register page.
(0448)
(0449) ; Dereference the constant (flash) pointer pXIData to access the start
(0450) ; of the extended idata area, "xidata." Xidata follows the end of the
(0451) ; text segment and may have been relocated by the Code Compressor.
(0452) ;
00E1: 50 01 MOV A,1 (0453) mov A, >__pXIData ; Get the address of the flash
00E3: 57 A0 MOV X,160 (0454) mov X, <__pXIData ; pointer to the xidata area.
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