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0019 PRT6DM1: equ 19h ; Port 6 Drive Mode 1 (RW)
001A PRT6IC0: equ 1Ah ; Port 6 Interrupt Control 0 (RW)
001B PRT6IC1: equ 1Bh ; Port 6 Interrupt Control 1 (RW)
0000
0000 ; Port 7
001C PRT7DM0: equ 1Ch ; Port 7 Drive Mode 0 (RW)
001D PRT7DM1: equ 1Dh ; Port 7 Drive Mode 1 (RW)
001E PRT7IC0: equ 1Eh ; Port 7 Interrupt Control 0 (RW)
001F PRT7IC1: equ 1Fh ; Port 7 Interrupt Control 1 (RW)
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 0.
0000 ;------------------------------------------------
0000
0000 ; Digital PSoC block 00, Basic Type B
0020 DBB00FN: equ 20h ; Function Register (RW)
0021 DBB00IN: equ 21h ; Input Register (RW)
0022 DBB00OU: equ 22h ; Output Register (RW)
0000
0000 ; Digital PSoC block 01, Basic Type B
0024 DBB01FN: equ 24h ; Function Register (RW)
0025 DBB01IN: equ 25h ; Input Register (RW)
0026 DBB01OU: equ 26h ; Output Register (RW)
0000
0000 ; Digital PSoC block 02, Communications Type B
0028 DCB02FN: equ 28h ; Function Register (RW)
0029 DCB02IN: equ 29h ; Input Register (RW)
002A DCB02OU: equ 2Ah ; Output Register (RW)
0000
0000 ; Digital PSoC block 03, Communications Type B
002C DCB03FN: equ 2Ch ; Function Register (RW)
002D DCB03IN: equ 2Dh ; Input Register (RW)
002E DCB03OU: equ 2Eh ; Output Register (RW)
0000
0000 ; Digital PSoC block 10, Basic Type B
0030 DBB10FN: equ 30h ; Function Register (RW)
0031 DBB10IN: equ 31h ; Input Register (RW)
0032 DBB10OU: equ 32h ; Output Register (RW)
0000
0000 ; Digital PSoC block 11, Basic Type B
0034 DBB11FN: equ 34h ; Function Register (RW)
0035 DBB11IN: equ 35h ; Input Register (RW)
0036 DBB11OU: equ 36h ; Output Register (RW)
0000
0000 ; Digital PSoC block 12, Communications Type B
0038 DCB12FN: equ 38h ; Function Register (RW)
0039 DCB12IN: equ 39h ; Input Register (RW)
003A DCB12OU: equ 3Ah ; Output Register (RW)
0000
0000 ; Digital PSoC block 13, Communications Type B
003C DCB13FN: equ 3Ch ; Function Register (RW)
003D DCB13IN: equ 3Dh ; Input Register (RW)
003E DCB13OU: equ 3Eh ; Output Register (RW)
0000
0000 ; Digital PSoC block 20, Basic Type B
0040 DBB20FN: equ 40h ; Function Register (RW)
0041 DBB20IN: equ 41h ; Input Register (RW)
0042 DBB20OU: equ 42h ; Output Register (RW)
0000
0000 ; Digital PSoC block 21, Basic Type B
0044 DBB21FN: equ 44h ; Function Register (RW)
0045 DBB21IN: equ 45h ; Input Register (RW)
0046 DBB21OU: equ 46h ; Output Register (RW)
0000
0000 ; Digital PSoC block 22, Communications Type B
0048 DCB22FN: equ 48h ; Function Register (RW)
0049 DCB22IN: equ 49h ; Input Register (RW)
004A DCB22OU: equ 4Ah ; Output Register (RW)
0000
0000 ; Digital PSoC block 23, Communications Type B
004C DCB23FN: equ 4Ch ; Function Register (RW)
004D DCB23IN: equ 4Dh ; Input Register (RW)
004E DCB23OU: equ 4Eh ; Output Register (RW)
0000
0000 ; Digital PSoC block 30, Basic Type B
0050 DBB30FN: equ 50h ; Function Register (RW)
0051 DBB30IN: equ 51h ; Input Register (RW)
0052 DBB30OU: equ 52h ; Output Register (RW)
0000
0000 ; Digital PSoC block 31, Basic Type B
0054 DBB31FN: equ 54h ; Function Register (RW)
0055 DBB31IN: equ 55h ; Input Register (RW)
0056 DBB31OU: equ 56h ; Output Register (RW)
0000
0000 ; Digital PSoC block 32, Communications Type B
0058 DCB32FN: equ 58h ; Function Register (RW)
0059 DCB32IN: equ 59h ; Input Register (RW)
005A DCB32OU: equ 5Ah ; Output Register (RW)
0000
0000 ; Digital PSoC block 33, Communications Type B
005C DCB33FN: equ 5Ch ; Function Register (RW)
005D DCB33IN: equ 5Dh ; Input Register (RW)
005E DCB33OU: equ 5Eh ; Output Register (RW)
0000
0000 ;------------------------------------------------
0000 ; System and Global Resource Registers
0000 ; Note: Also see this address range in Bank 0.
0000 ;------------------------------------------------
0000
0060 CLK_CR0: equ 60h ; Analog Column Clock Select Register 0 (RW)
00C0 CLK_CR0_ACOLUMN_3: equ 0C0h ; MASK: Specify clock for analog cloumn
0030 CLK_CR0_ACOLUMN_2: equ 30h ; MASK: Specify clock for analog cloumn
000C CLK_CR0_ACOLUMN_1: equ 0Ch ; MASK: Specify clock for analog cloumn
0003 CLK_CR0_ACOLUMN_0: equ 03h ; MASK: Specify clock for analog cloumn
0000
0061 CLK_CR1: equ 61h ; Analog Clock Source Select Register 1 (RW)
0040 CLK_CR1_SHDIS: equ 40h ; MASK: Sample and Hold Disable (all Columns)
0038 CLK_CR1_ACLK1: equ 38h ; MASK: Digital PSoC block for analog source
0007 CLK_CR1_ACLK2: equ 07h ; MASK: Digital PSoC block for analog source
0000
0062 ABF_CR0: equ 62h ; Analog Output Buffer Control Register 0 (RW)
0080 ABF_CR0_ACOL1MUX: equ 80h ; MASK: Analog Column 1 Mux control
0040 ABF_CR0_ACOL2MUX: equ 40h ; MASK: Analog Column 2 Mux control
0020 ABF_CR0_ABUF1EN: equ 20h ; MASK: Enable ACol 1 analog buffer (P0[5])
0010 ABF_CR0_ABUF2EN: equ 10h ; MASK: Enable ACol 2 analog buffer (P0[4])
0008 ABF_CR0_ABUF0EN: equ 08h ; MASK: Enable ACol 0 analog buffer (P0[3])
0004 ABF_CR0_ABUF3EN: equ 04h ; MASK: Enable ACol 3 analog buffer (P0[2])
0002 ABF_CR0_BYPASS: equ 02h ; MASK: Bypass the analog buffers
0001 ABF_CR0_PWR: equ 01h ; MASK: High power mode on all analog buffers
0000
0063 AMD_CR0: equ 63h ; Analog Modulator Control Register 0 (RW)
0070 AMD_CR0_AMOD2: equ 70h ; MASK: Modulation source for analog column 2
0007 AMD_CR0_AMOD0: equ 07h ; MASK: Modulation source for analog column 1
0000
0066 AMD_CR1: equ 66h ; Analog Modulator Control Register 1 (RW)
0070 AMD_CR1_AMOD3: equ 70h ; MASK: Modulation ctrl for analog column 3
0007 AMD_CR1_AMOD1: equ 07h ; MASK: Modulation ctrl for analog column 1
0000
0067 ALT_CR0: equ 67h ; Analog Look Up Table (LUT) Register 0 (RW)
00F0 ALT_CR0_LUT1: equ 0F0h ; MASK: Look up table 1 selection
000F ALT_CR0_LUT0: equ 0Fh ; MASK: Look up table 0 selection
0000
0068 ALT_CR1: equ 68h ; Analog Look Up Table (LUT) Register 1 (RW)
00F0 ALT_CR1_LUT3: equ 0F0h ; MASK: Look up table 3 selection
000F ALT_CR1_LUT2: equ 0Fh ; MASK: Look up table 2 selection
0000
0069 CLK_CR2: equ 69h ; Analog Clock Source Control Register 2 (RW)
0008 CLK_CR2_ACLK1R: equ 08h ; MASK: Analog Clock 1 selection range
0001 CLK_CR2_ACLK0R: equ 01h ; MASK: Analog Clock 0 selection range
0000
0000 ;------------------------------------------------
0000 ; Global Digital Interconnects
0000 ;------------------------------------------------
0000
00D0 GDI_O_IN: equ 0D0h ; Global Dig Interconnect Odd Inputs Reg (RW)
00D1 GDI_E_IN: equ 0D1h ; Global Dig Interconnect Even Inputs Reg (RW)
00D2 GDI_O_OU: equ 0D2h ; Global Dig Interconnect Odd Outputs Reg (RW)
00D3 GDI_E_OU: equ 0D3h ; Global Dig Interconnect Even Outputs Reg (RW)
0000
0000 ;------------------------------------------------
0000 ; Clock and System Control Registers
0000 ;------------------------------------------------
0000
00DD OSC_GO_EN: equ 0DDh ; Oscillator to Global Outputs Enable Register (RW)
0080 OSC_GOEN_SLPINT: equ 80h ; Enable Sleep Timer onto GOE[7]
0040 OSC_GOEN_VC3: equ 40h ; Enable VC3 onto GOE[6]
0020 OSC_GOEN_VC2: equ 20h ; Enable VC2 onto GOE[5]
0010 OSC_GOEN_VC1: equ 10h ; Enable VC1 onto GOE[4]
0008 OSC_GOEN_SYSCLKX2: equ 08h ; Enable 2X SysClk onto GOE[3]
0004 OSC_GOEN_SYSCLK: equ 04h ; Enable 1X SysClk onto GOE[2]
0002 OSC_GOEN_CLK24M: equ 02h ; Enable 24 MHz clock onto GOE[1]
0001 OSC_GOEN_CLK32K: equ 01h ; Enable 32 kHz clock onto GOE[0]
0000
00DE OSC_CR4: equ 0DEh ; Oscillator Control Register 4 (RW)
0003 OSC_CR4_VC3: equ 03h ; MASK: System VC3 Clock source
0000
00DF OSC_CR3: equ 0DFh ; Oscillator Control Register 3 (RW)
0000
00E0 OSC_CR0: equ 0E0h ; System Oscillator Control Register 0 (RW)
0080 OSC_CR0_32K_SELECT: equ 80h ; MASK: Enable/Disable External XTAL Osc
0040 OSC_CR0_PLL_MODE: equ 40h ; MASK: Enable/Disable PLL
0020 OSC_CR0_NO_BUZZ: equ 20h ; MASK: Bandgap always powered/BUZZ bandgap
0018 OSC_CR0_SLEEP: equ 18h ; MASK: Se⌨️ 快捷键说明
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